[SI-LIST] Re: [SI-LIST]: Which tool is the best - LINPARdisc ussion
- From: "Muranyi, Arpad" <arpad.muranyi@xxxxxxxxx>
- To: "Chris Cheng" <Chris.Cheng@xxxxxxxxxxxx>, <si-list@xxxxxxxxxxxxx>
- Date: Thu, 29 Apr 2004 01:01:57 -0700
Chris,
I do not want to react to every single thought in your message, but I
feel
(for the sake of the rest of the readers) that I should mention that the
situation is not as bad as you paint it.
It is true that in the past IBIS lagged behind the bleeding edge
technology
because it took so long to come up with new keywords for the new
behaviors
in the latest buffer types (such as GTL). However, now that we have
these
new language extensions, the IBIS specification will not have to be
"tailored"
to every new buffer behavior that designers com up with. It will be
only
up to the model maker how long it will take to see a behavioral model
for
a new buffer design.
Second, I can understand many of your reasons that you makes you want to
stick
with transistor level models. However, don't forget that these
behavioral
models can run much faster than full transistor level models, I measured
close to 300x speed improvements on one of the PCI-express designs. If
you
want to run thousands of signal integrity simulations with a model that
takes 30 minutes (or more) for each run you will never get your work
done...
Arpad
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-----Original Message-----
From: Chris Cheng [mailto:Chris.Cheng@xxxxxxxxxxxx]=20
Sent: Tuesday, April 27, 2004 11:53 AM
To: Muranyi, Arpad; si-list@xxxxxxxxxxxxx
Subject: RE: [SI-LIST] Re: [SI-LIST]: Which tool is the best -
LINPARdisc ussion
Sure, anything is possible. And the dog ate my homework.
Just kidding. Little bird always reminds me that those are very smart
people and he is always grateful for the work they have done. And I am
told at least one of them got it reasonably fast on first try.
=20
I never got paid to create industry standards or sell CAD tools.My
current or former employers just pay me to make sure their own or
customers systems work. Very smart circuit designers gave me very smart
I/O. I am just lucky to even have a circuit description of it. To ask me
to generate an accurate behavioral abstraction of it everytime something
new comes out is beyond my limited intelligence. Case and point is the
original GTL driver by Bill Gunning with the delay feedback for my first
GTL system, I can't even remember how long did it take (or if ever) for
IBIS to be able to generate an accurate model of it. And if at the end
of the day those so call tools "will get better in the future" or "be
able to do what you want in the next rev" or "add x tool to y tool and
you may be able to do that", that's just too complicated for me.
Remember, I am just a dumb engineer who wants one tool to do it all.
Seems like I've been lucky so far with what I've got and I'll probably
stick with it for awhile.
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