[SI-LIST] Re: [SI-LIST]: Which tool is the best - LINPARdisc ussion
- From: "Muranyi, Arpad" <arpad.muranyi@xxxxxxxxx>
- To: <si-list@xxxxxxxxxxxxx>
- Date: Sun, 25 Apr 2004 21:51:33 -0700
Chris,
I don't think any of us IBIS proponents ever claimed that IBIS models
were capable of modeling receivers as you like to use them. That was
something that traditional IBIS did not cover, period.
However, now that the IBIS 4.1 specification added the VHDL-AMS and
Verilog-AMS language extensions, we actually DO have the capability
to write behavioral models to even do that, if you like.
Arpad Muranyi
Intel Corporation
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
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-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
On Behalf Of Chris Cheng
Sent: Friday, April 23, 2004 5:36 PM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: [SI-LIST]: Which tool is the best - LINPARdisc
ussion
The problem is not just what the differential waveform looks like at the
receiver after the interconnect. There are very subtle common mode
variation at the receiver that can impact the OUTPUT of these multi-Gb/s
receivers some of which have very limited common mode range.
Those who know me should know how anal I am to define I/O timing at the
OUTPUT of the receiver rather than the input. Try that on your IBIS
model.
To add more fun, try that with those built-in multi-stage equalizing
receivers.
Any smart IBIS proponent out there can show me how to model that ?
-----Original Message-----
From: George Tang [mailto:gtang@xxxxxxxx]
Sent: Friday, April 23, 2004 5:22 PM
To: Chris.Cheng@xxxxxxxxxxxx; steven.corey@xxxxxxxxxxxxxx;
si-list@xxxxxxxxxxxxx
Subject: RE: [SI-LIST] Re: [SI-LIST]: Which tool is the best -
LINPARdisc ussion
Chris,
You are exactly right. In a simulation, there are certain parts of your
system which dominates the simulation time, i.e.., the transistor
models.
But there are also certain parts of your system that dominates the
system performance. For example, after you finish your system
simulation with the actual drivers, you can replace the transistor
driver model with an ideal driver with a fixed rise-time and output
impedance. If you vary the rise-time from 30ps to 50ps to 70ps, you may
find that after 35 inches in
FR4 and a few connectors, the resulting waveforms are almost the same (
> 1ns rise-time). Only in this case, you can choose to use a simplified
driver in place of the transistor model. But you are right. In
general, transistor level models are always preferred for better
accuracy.
Kind regards,
George
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx
[mailto:si-list-bounce@xxxxxxxxxxxxx]On Behalf Of Chris Cheng
Sent: Friday, April 23, 2004 3:08 PM
To: 'steven.corey@xxxxxxxxxxxxxx'; 'si-list@xxxxxxxxxxxxx'
Subject: [SI-LIST] Re: [SI-LIST]: Which tool is the best - LINPARdisc
ussion
Totally agree.
The key is cross check the model with measurement and trusted field
solver results.
Like I said before, my personal favorite tool is ADS which has all the
distributed, lumped and S-param models you want. However, once in a
while I have encrypted HSPICE model from vendors that forces me to
switch back to HSPICE. As mentioned in another thread, I have zero faith
in the field solver W element in HSPICE. That leaves me with either
paying a few $$K for an expensive field solver tool or using Linpar.
I'll take the later anyday.
But I can always calibrate the interconnect models with ADS before using
it in full circuit simulations.
While there are very smart people here that claim they can simulate
multi-Gb/s I/O's with IBIS. I am just too dumb to do so and I only trust
full transistor level SPICE I/O models. With that, you can pretty much
ignore any impact of your interconnect models on your simulation time.
-----Original Message-----
From: Steve Corey [mailto:steven.corey@xxxxxxxxxxxxxx]
Sent: Friday, April 23, 2004 2:14 PM
To: 'si-list@xxxxxxxxxxxxx'
Subject: [SI-LIST] Re: [SI-LIST]: Which tool is the best - LINPARdisc
ussion
Chris -- I break "bad" approximations into roughly two categories:
1. inaccurate fit to the measured data
2. non-passivity
#1 can be quantified prior to running system simulations by comparing
against measurements or trusted field-solver results. If a rational
approximation algorithm breaks down, it will show up as #1.
#2 tends to result in more catastrophic failure, such as oscillation or
exponential growth. However, the oscillations may not be crazy enough
to cross your personal threshold, and those are probably the most
insidious. The best approach is to guarantee #2 mathematically prior to
simulation, especially if you're a model provider.
If you've convinced yourself that interconnects aren't contributing
heavily to your simulation time, you're probably right. It definitely
depends on the nature of the system you're simulating. In the question
of lumped (i.e., rational approximation) vs. distributed models, we
aren't apologists for any particular approach. We provide the ability
to extract both, and let the user determine which is more appropriate
based on the application.
-- Steve
-------------------------------------------
Steven D. Corey, Ph.D.
Time Domain Analysis Systems, Inc.
"The Interconnect Analysis Company."
http://www.tdasystems.com
email: steven.corey@xxxxxxxxxxxxxx
phone: (503) 246-2272
fax: (503) 246-2282
-------------------------------------------
Chris Cheng wrote:
> Steve,
> My question is, if the approximation is bad, what does it exhibit=20
> itself
in
> the simulation ?
> If it results in "internal time step too small" or crazy oscillation,=20
> I
know
> immediately the model has problem and move on. If however, it=20
> generates
the
> wrong waveform with incorrect delay, I will be very worry.
> Interconnect model impact on simulation memory and time is not a=20
> concern
for
> me, I believe my I/O circuits and package models dominates that by
far.
>
> -----Original Message-----
> From: Steve Corey [mailto:steven.corey@xxxxxxxxxxxxxx]
> Sent: Friday, April 23, 2004 8:43 AM
> To: 'si-list@xxxxxxxxxxxxx'
> Subject: [SI-LIST] Re: [SI-LIST]: Which tool is the best - LINPARdisc=20
> ussion
>
>
> Ray -- although your statement is correct, it is numerically difficult
> to achieve. Not all algorithms are robust enough to fit long, nearly=20
> lossless delays. Furthermore, simulations of electrically large,=20
> nearly lossless systems take longer as well. How to extract delay and
> treat it separately when fitting such data is a current area of
research.
>
> Of course, this phenomena isn't isolated to rational approximations,=20
> but is a general problem with stiff systems -- those which have both=20
> microscopic and macroscopic behaviors excited simultaneously. A long=20
> cable with little loss driven with a fast-risetime signal is a good=20
> example. As a broad generalization, the wider the range of behaviors=20
> being simulated, the more memory and time that will be required to=20
> simulate it.
>
> Different simulation and modeling techniques are optimized for=20
> different types of systems. For example, good distributed=20
> transmission line models are often better for simulating long=20
> transmission lines at fast risetimes than are straight rational
approximations.
>
> -- Steve
>
> -------------------------------------------
> Steven D. Corey, Ph.D.
> Time Domain Analysis Systems, Inc.
> "The Interconnect Analysis Company."
> http://www.tdasystems.com
>
> email: steven.corey@xxxxxxxxxxxxxx
> phone: (503) 246-2272
> fax: (503) 246-2282
> -------------------------------------------
>
>
> Raymond Anderson wrote:
>
>>Raj Raghuram wrote:
>>
>>
>>
>>>>I am not sure modeling with S-params would work for long=20
>>>>transmission lines i.e. metres in length. Most s-parameter=20
>>>>simulators use a rational fit which in the end is a lumped model.
Maybe you can comment on this.
>>>>
>>>>
>>>
>>
>>The delay information required to model an electrically long structure
>>such as a transmission line is contained in the phase information of=20
>>the complex s-parameters.
>>
>>Most instruments output the phase of s-parameters in the range of +180
>>to -180 degrees. Plotted wrt frequency it resembles a sawtooth. This=20
>>modulo 360 phase info needs to be unwrapped into a linear phase=20
>>progression to interpret it as delay.
>>
>>When a rational polynomial approximation is fitted to the unwrapped=20
>>s-parameter data, if the phase part of the approximation is the same=20
>>as the phase of the original s-parameter then I'd expect the resultant
>>macromodel to exhibit the same delay characteristics.
>>
>>Comments ???
>>
>>
>>-Ray Anderson
>>
>>Sun Microsystems Inc.
>>
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