[SI-LIST] Re: Reducing SSO noise in an FPGA
- From: "Bradley S Henson" <bhenson@xxxxxxxxxxxx>
- To: cgrassosprint1@xxxxxxxxxxxxx
- Date: Wed, 16 Jul 2003 06:42:12 -0700
Charles,
It is "normal" to see many types of drivers with this magnitude of
switching current. The manufacturers list a low-current value for which
they guarantee a static Voh or Vol. 4mA is historically used quite a bit.
However, it has almost nothing to do with the dynamic switching current you
will see in sims or practice.
If you extract the IV characteristics of your driver and superimpose a load
line with the value of your transmission line across it, you will get the
magnitude of the launch voltage and current sourced (or sunk) by the
driver. 40mA is very typical for modern LVCMOS type technology. If you see
a 2V incident wave launched from a driver onto a 50 ohm T-line, then you
know that the driver sourced or sunk 40mA when it switched. With strong
drivers and low impedance transmission lines (i.e., multidrop bus), you can
see 100mA, perhaps more. With a large enough lumped capacitance near the
output you will approach the Ios, short circuit current, of the driver. Ios
can be 200mA for some drivers.
Hope this helps,
Brad Henson
Raytheon
"Charles Grasso"
<cgrassosprint1@ear To:
<Ken.Cantrell@xxxxxxxxxxx>,
thlink.net> <chris.cheng@xxxxxxxxxxxx>,
"'Fabrizio Zanella'"
Sent by: <fzanella@xxxxxxxxxxxx>
si-list-bounce@free cc:
<si-list@xxxxxxxxxxxxx>
lists.org Subject: [SI-LIST] Re:
Reducing SSO noise in an FPGA
07/15/2003 10:12 PM
Please respond to
cgrassosprint1
Hi Ken - I have a Q on this.
I have done simulations on BGAs and looked at the
current waveforms that the sims predict. Instead of the
*wimpy* 5mA or so that the manf puts in the data
sheets, I am observing >40mA at the switching
transitions. I put this down to primarily the
momentary short that exists as the device chages state.
Have you (or others) similar experiences or are the
data sheets accurate?
Incidentally as an EMI guy the >40mA is extremely
interesting to me..!!
Charles Grasso
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx
[mailto:si-list-bounce@xxxxxxxxxxxxx]On Behalf Of Ken Cantrell
Sent: Tuesday, July 15, 2003 1:21 PM
To: chris.cheng@xxxxxxxxxxxx; 'Fabrizio Zanella'
Cc: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: Reducing SSO noise in an FPGA
Or go to a class 1 if you are using a class 2 (7.2 mA vs 15.7 ma)
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx
[mailto:si-list-bounce@xxxxxxxxxxxxx]On Behalf Of Chris Cheng
Sent: Tuesday, July 15, 2003 2:09 PM
To: 'Fabrizio Zanella'; Chris Cheng
Cc: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: Reducing SSO noise in an FPGA
Sure you can, don't you have an external series resistor and parallel
terminator you can play around their values ?
-----Original Message-----
From: Fabrizio Zanella [mailto:fzanella@xxxxxxxxxxxx]
Sent: Tuesday, July 15, 2003 12:58 PM
To: chris.cheng@xxxxxxxxxxxx
Cc: si-list@xxxxxxxxxxxxx
Subject: RE: [SI-LIST] Re: Reducing SSO noise in an FPGA
I cannot reduce the drive strength, the drivers are SSTL2. We reduced
the SSO noise significantly by turning off half the data bits.
-----Original Message-----
From: Chris Cheng [mailto:chris.cheng@xxxxxxxxxxxx]
Sent: Tuesday, July 15, 2003 2:27 PM
Cc: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: Reducing SSO noise in an FPGA
What's wrong with reducing the driving strength of the drivers in the
FPGA ?
Are you at the limit of the lowest possible drive strength already ?
-----Original Message-----
From: Fabrizio Zanella [mailto:fzanella@xxxxxxxxxxxx]
Sent: Tuesday, July 15, 2003 5:54 AM
To: bhenson@xxxxxxxxxxxx; Ken.Cantrell@xxxxxxxxxxx
Cc: bill.panos@xxxxxxxxxxxxxxx; Chris Cheng; scott@xxxxxxxxxxxxx;
si-list@xxxxxxxxxxxxx
Subject: RE: [SI-LIST] Re: Reducing SSO noise in an FPGA
This discussion has turned quite interesting. There have been several
comments which imply that the only way to reduce SSO noise in an
FPGA/ASIC is to add decoupling at the die or inside the package. These
are fixes which only the device manufacturers can make.
Does anyone have measurement/simulation data on what effect adding many
decoupling capacitors under the BGA package, between VCC and ground
balls, will have on the SSO noise?
Thanks and regards,
Fabrizio
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