[SI-LIST] Re: Reducing SSO noise in an FPGA
- From: Scott McMorrow <scott@xxxxxxxxxxxxx>
- To: fzanella@xxxxxxxxxxxx
- Date: Thu, 26 Jun 2003 15:21:16 -0700
Fabrizio,
By now, you've heard many interesting comments, some of which are very
good, but none of which gives the entire picture.
The SSN problem can be divided to the following parts that I can think
of off the top of my head:
1) Power delivery to the I/O drivers.
2) Signal mode conversion at the die/package substrate boundary.
3) Signal mode conversion at the package/board boundary.
4) Device output impedance matching.
5) Package forward and reverse crosstalk.
6) Board decoupling.
7) Power/ground plane perforation due to antipads.
1) Anything that reduces loop inductance from the die, through the
package and to the PCB planes, reduces the SSN effects on power
delivery. Select your packages with good I/O power rail and ground
ballout patterns.
2) You can't do a darn thing about this, since the FPGA manufacturer
takes control of this part of the design. However, how the die is
escaped to the package, and which power planes the signals are routed
adjacent to, has a huge impact on SSN. If you have a choice, spread
your output signals across a wide area of the package, rather than a
narrow area or section, as this will distribute the signaling currents
across the package.
3) Match the planes that your signals are referenced to to the same
reference planes that are used in the package. You'll have to query the
manufacturer regarding this, and you may not obtain the data,
unfortunately. By matching planes, you will keep a continuous return
path as the signals exits the package and enters your board. You will
reduce your noise greatly by doing this. In addition, since there is
normally a ground and a power rail supplying current to the I/O driver,
You would optimally like to place a power ground plane pair next to
your signal layers to provide the best high frequency decoupling and
mode conversion control.
4) Select the slowest driver output and whenever possible impedance
match the driver to the board trace impedance. Better yet, match the
driver to the package trace impedance, and match the trace impedance of
the board to your package.. A matched driver will terminate any
crosstalk from neighbor lines and reduce the impact of reflected reverse
crosstalk in the package. If your drivers are low impedance and the
package is poorly designed (not uncommon in the FPGA world) and if the
driver edge rate is extremely fast, reverse crosstalk from adjacent
lines can reach total saturation within the package, reflect off the
driver, and become launched onto the external. system traces. In fact,
for fast edges and poorly designed packages with higher crosstalk
coeffieients than the PCB trace, it is entirely possible for stripline
traces to build up maximum crosstalk before the signal ever reaches the
board. In this case, all your good work at controlling PCB level
coupling is all for naught.
5) See #4 ... if you have a choice, have the data available from the
manufacturer, or can measure it yourself, choose the package with the
lowest crosstalk.
6) Your decoupling capacitors will have an impact on noise reduction at
the fundamental switching frequency of the bus, but they are not close
enough to impact the SSN due to 128 simultaneous drivers switching.
Your decoupling capacitors, due to the time delay between the die and
the capacitors, will only have an impact on the long term average noise.
So, use your capacitors to decouple the planes. Follow the breakout
recommendations of the many guys from Sun who have given us all such
wonderful theoretical and practical work and advice on decoupling. You
can make the noise worse by not following their guidelines and advise,
but you will not solve problems inherent to SSN within a package.
7) Use the smallest antipad size that you can get away with to reduce
the amount of plane perforation. Push your manufacturing process to use
the absolute minimum size via hole, pad and antipad for signal vias.
Finally, if you are designing your own custom bus, rather than
interfacing to an existing bus, then roll-your-own balanced coding
scheme to limit the number simultaneous signal transitions on the bus.
best regards,
scott
--
Scott McMorrow
Teraspeed Consulting Group LLC
2926 SE Yamhill St.
Portland, OR 97214
(503) 239-5536
http://www.teraspeed.com
Fabrizio Zanella wrote:
>I would like to hear about experiences regarding methods of reducing
>simultaneous switching noise in a large FPGA, BGA package. Let's assume
>a 128bit bus, with a signal frequency of 100MHz.
>How effective is adding ground planes 2 mils from the VCC planes in
>reducing SSN? If one uses BC, does every VCC pin in the FPGA require
>decoupling? And should the caps be tied to the BGA pins with blind vias
>so they can be placed directly under the BGA? What are the optimal
>values for the decoupling capacitors, 0.1uf, 0.22uF?
>
>Thanks very much and regards,
>
>
>Fabrizio Zanella
>Principal Hardware Design Engineer
>Broadbus Technologies
>fzanella@xxxxxxxxxxxx
>=20
>
>
------------------------------------------------------------------
To unsubscribe from si-list:
si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field
or to administer your membership from a web page, go to:
//www.freelists.org/webpage/si-list
For help:
si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field
List archives are viewable at:
//www.freelists.org/archives/si-list
or at our remote archives:
http://groups.yahoo.com/group/si-list/messages
Old (prior to June 6, 2001) list archives are viewable at:
http://www.qsl.net/wb6tpu
Other related posts:
