[SI-LIST] Re: Reducing SSO noise in an FPGA
- From: stephanie.goedecke@xxxxxxxxxxx
- To: <si-list@xxxxxxxxxxxxx>
- Date: Mon, 30 Jun 2003 09:34:28 +0200
Hello Fabrizio,
I have a non-conventional solution that worked for me here with SSTL2 SSO noise.
I will share it in case it is helpful to you. (It might not be).
In this application, I replaced the standard SSTL2 termination scheme with a
single
50 Ohm series resistor, and no parallel resistor, on all of the signals. This
is except
for the clock, which now has 33 Ohm series, and 100 Ohm parallel resistors, to
increase its signal swing from what it was. All of these signals are
point-to-point.
These changes reduced the current flow for each signal transition enough to
solve
the SSO problems we were seeing. The termination mismatches, and slight timing
delays caused, are not a problem for this case. But they might be a problem
where traces are longer, or frequencies are higher.
regards,
Stephanie
Stephanie Goedecke
Philips - SP3D Chip Design GmbH
Petersbrunnerstr.17
82319 Starnberg / Germany
Phone: +49-8151-270-160
Fax : +49-8151-270-200
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