[SI-LIST] Reducing SSO noise in an FPGA
- From: Gregory R Edlund <gedlund@xxxxxxxxxx>
- To: fzanella@xxxxxxxxxxxx, si-list@xxxxxxxxxxxxx
- Date: Thu, 26 Jun 2003 08:18:31 -0500
Hey Fabrizio,
I've always thought about SSO noise and decoupling as separate problems,
i.e. design your power distribution system to some ripple spec (say 5% of
Vdd) and then make sure your quiet line SSO noise never gets larger than
some limit (say 20% of Vdd). In my mind, these numbers are always a
determined by my noise budget - keeping in mind that worst-case SSO noise
and worst-case bus timing usually don't coincide. My method may be a bit
old-fashioned, and you bring up an interesting point: can you analyze
these two problems together? I am not aware of a tool that can do this.
I've always used SPICE for SSO analysis of wire bonded packages, and Speed
seems to be the most sophisticated tool for analyzing the complex
decoupling problem. I don't put a whole lot of stock in simplistic,
back-of-the-envelope decoupling theories because they have led me astray in
the past.
From what you've said about your particular problem, it sounds like a
classical SSO problem that will be dominated by the bond wire inductance
and the driver di/dt, assuming you have a solid PSD leading up to the
package. Therefore, focus on getting the right signal-to-return ratio when
you assign the chip I/Os, and don't use a driver that is any faster than
you absolutely need it to be. And of course, watch out for those IBIS
models of drivers that have some kind of whiz-bang compensation circuitry!
By the way, I have found that measuring SSO noise at the far end of a quiet
line is the best way to confirm the goodness of your design. This assumes
you have some way of forcing one of the signals on your bus to be static
for a period of time while every other signal is switching.
Cheers,
Greg Edlund
Senior Engineer
Signal Integrity
IBM Engineering and Technology Services
3605 Hwy. 52 N, Dept. HDC
Rochester, MN 55901
gedlund@xxxxxxxxxx
Msg: #1 in digest
Subject: [SI-LIST] Reducing SSO noise in an FPGA
Date: Wed, 25 Jun 2003 12:01:31 -0400
From: "Fabrizio Zanella" <fzanella@xxxxxxxxxxxx>
I would like to hear about experiences regarding methods of reducing
simultaneous switching noise in a large FPGA, BGA package. Let's assume
a 128bit bus, with a signal frequency of 100MHz.
How effective is adding ground planes 2 mils from the VCC planes in
reducing SSN? If one uses BC, does every VCC pin in the FPGA require
decoupling? And should the caps be tied to the BGA pins with blind vias
so they can be placed directly under the BGA? What are the optimal
values for the decoupling capacitors, 0.1uf, 0.22uF?
Thanks very much and regards,
Fabrizio Zanella
Principal Hardware Design Engineer
Broadbus Technologies
fzanella@xxxxxxxxxxxx
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