[SI-LIST] Re: PCB thickness
- From: "Bill Hargin \(In-Circuit Design\)" <b.hargin@xxxxxxxxxx>
- To: <b.hargin@xxxxxxxxxx>, <hitheshn@xxxxxxxxx>, "'Nobuyuki Kunito'" <kunito@xxxxxxxxxxx>
- Date: Sat, 2 Feb 2013 12:23:35 -0800
I didn't know how that was going to look after passing through the server
... This may be a little better. Paste it into a text editor to get all of
the columns to line up. (Sorry ... This is all in mils ... If you download
the eval software, it's easy to toggle back and forth between mils and
microns.)
Lyr Description Lyr Name Dk(Er) T S Width Zo Zdiff
Soldermask 3.3 0.5
1 Signal Top 1.2 12 6.5 52 99
Prepreg 4.0 4
2 Plane ----- GND ------------- 1.2
Core 4.0 6
3 Signal Inner 3 1.2 12 4.5 52 101
Prepreg 4.0 8
4 Plane ----- VCC ------------- 1.2
Core 4.0 3.0 << INTERPLANE CAPACITANCE
5 Plane ----- GND ------------- 1.2
Prepreg 4.0 8
6 Signal Inner 6 1.2 12 4.5 52 101
Core 4.0 6
7 Plane ----- VDD ------------- 1.2
Prepreg 4.0 8
8 Signal Inner 8 1.2 12 4.5 52 101
Core 4.0 6
9 Plane ----- GND ------------- 1.2
Prepreg 4.0 4
10 Signal Bottom 1.2 12 6.5 52 99
Soldermask 3.3 0.5
Total Board Thickness=61.4 mil
Differential Signals: Zdiff=90 ohms
Layer Spacing Width Zo Zdiff
1 12 7.5 48.27 91.74
3 12 5.5 47.53 92.26
6 12 5.5 47.53 92.26
8 12 5.5 47.53 92.26
10 12 7.5 48.27 91.74
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On
Behalf Of Bill Hargin (In-Circuit Design)
Sent: Saturday, February 02, 2013 11:55 AM
To: hitheshn@xxxxxxxxx; 'Nobuyuki Kunito'
Cc: 'SI-List'
Subject: [SI-LIST] Re: PCB thickness
Hi Hithesh:
There are a number of issues with your stackup; and I believe that all of
them can be remedied by going to 10 layers, and adding 2 more planes.
Instead of doing what my wife wanted me to do this Saturday morning, I
decided to play with your stackup ...
- Impedance: With your current stackup, I agree with your fab house, in the
sense that there's no place to add board thickness while maintaining target
impedances. (Not enough layers.)
- Board Thickness: Any particular reason you're targeting 1.6mm (62mils)?
If you're not dealing with an edge connector that needs a 1.6mm thickness,
there would need to be a compelling reason to worry about it. I realize
that some fabs have tooling that's all set up for 62mils, and that they may
charge more to
- Asymmetry: Did your fab house mention that your stackup is asymmetrical?
They should have mentioned that, in addition to the thickness/impedance
discussion. Asymmetrical stackups can lead to warping; and warping can lead
to open circuits at vias, for example.
- Educational stuff: Lee Ritchey talks about all of the above in his "Right
the First Time" books. I put on a webinar series that covers all of this,
as well. You can sign up for it on
http://www.icd.com.au/Webinars-PCB-Stackup-Technology-Series.html
It's a bit unusual to see a board with 5 signal layers and only 3 reference
planes. For the small cost of going to 10 layers (5 signals; 5 planes), you
can improve signal integrity, crosstalk, power distribution, and EMI -
probably saving yourself a lot of headaches down the road. Based on all of
this, and your comment about USB and DDR2 signals, I would recommend the
following stackup (Im playing with an ASCII-output capability for our
Stackup Planner tool; paste into a text editor to make it more readable ...
If you want to visualize this better, download our [free] eval software from
http://www.icd.com.au/FX.html, and I'll send you the before/after files for
your stackup):
Lyr Description Lyr Name Matl Type Dk(Er) Thickness Spacing Width Zo
Zdiff
Soldermask Dielectric 3.3 0.5
1 Signal Top Conductive 1.2 12 6.5
51.99 98.74
Prepreg Dielectric 4.0 4
2 Plane ----- GND ----- Conductive -------- 1.2
Core Dielectric 4.0 6
3 Signal Inner 3 Conductive 1.2 12 4.5
51.96 100.6
Prepreg Dielectric 4.0 8
4 Plane ----- VCC ----- Conductive -------- 1.2
Core Dielectric 4.0 3.0 <<<<<
INTERPLANE CAPACITANCE (FOR SSO)
5 Plane ----- GND ----- Conductive -------- 1.2
Prepreg Dielectric 4.0 8
6 Signal Inner 6 Conductive 1.2 12 4.5
51.96 100.6
Core Dielectric 4.0 6
7 Plane ----- VDD ----- Conductive -------- 1.2
Prepreg Dielectric 4.0 8
8 Signal Inner 8 Conductive 1.2 12 4.5
51.96 100.6
Core Dielectric 4.0 6
9 Plane ----- GND ----- Conductive -------- 1.2
Prepreg Dielectric 4.0 4
10 Signal Bottom Conductive 1.2 12 6.5
51.99 98.74
Soldermask Dielectric 3.3 0.5
Total Board Thickness=61.4 mil
Differential Signals: Zdiff=90 ohms
Layer Spacing Width Zo Zdiff
1 12 7.5 48.27 91.74
3 12 5.5 47.53 92.26
6 12 5.5 47.53 92.26
8 12 5.5 47.53 92.26
10 12 7.5 48.27 91.74
* I assumed Dk=4.0. You would need to have more info on the materials on
hand with your fab to refine the thicknesses and Dk's.
Bill Hargin
In-Circuit Design, USA
Software & SI Simulation for High-Speed PCB Design
(425) 301-4425 b.hargin@xxxxxxxxxx Skype: bill.hargin
Online: www.icd.com.au
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On
Behalf Of Hithesh
Sent: Saturday, February 02, 2013 12:11 AM
To: Nobuyuki Kunito
Cc: SI-List
Subject: [SI-LIST] Re: PCB thickness
Hi,
It's an 8 layer board.
Stack up below
L1: Fan out/GND
L2: GND
L3: Sig
L4: PWR
L5: Sig
L6: Sig
L7: GND
L8: Fan out/GND
The Cu thickness is 1oz on inner layers and 1oz finished thickness on outer
layers.
The Er/dielectric is left to the fab house.
The board has high speed USB diff signals and DDR2 (133MHz).
We use different Fab house for protos and production. The proto Fab house
did not have any difficulty achieving board thickness and our impedance
requirement. But the production Fab house wants to reduce PCB thickness and
modify dielectric thickness.
Regards
-Hithesh
On Sat, Feb 2, 2013 at 1:32 PM, Nobuyuki Kunito <kunito@xxxxxxxxxxx> wrote:
> Hithesh,
>
> First of all, please tell us:
> How many layers the PCB have?
> Layer construction and/or stack up (the thickness of metal, dielectric
> material and Er of each dielectric material etc.) I am guessing that
> the PCB fib house may change the dielectric material..
>
> Please give us the information above first.
>
> Regards,
> Nobuyuki Kunito.
> The president of Debug Lab.
> http://debuglab.jp
> (Sorry, Japanese only now. English page will be coming soon)
>
> (2013/02/02 15:17), Hithesh wrote:
> > Hi,
> > What is the impact of changing PCB thickness?
> > To cut a long story short, the PCB fab house we use said they can't
> > meet our impedance requirement and achieve board thickness of 1.6mm.
> > They have to reduce the board thickness to 1.13mm to meet impedance
> > requirement.
> > He did say they could achieve both when we sent them the stack up pdf.
> But
> > now they said they can't take decisions just based on stack up.
> >
> > Regards
> > -Hithesh
> >
> >
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