[SI-LIST] Re: On-die caps for IO supply
- From: "Steve Waldstein" <swldstn@xxxxxxxxxxxx>
- To: "'Lee Ritchey'" <leeritchey@xxxxxxxxxxxxx>, "'Chris Cheng'" <Chris.Cheng@xxxxxxxx>, "'Stephane Tremblay'" <strembl1@xxxxxxxxxx>, <si-list@xxxxxxxxxxxxx>
- Date: Thu, 10 Apr 2008 19:14:41 -0400
Steph,
Rules of thumb are OK but I'd recommend creating a PCB/Package/Die model of
your IO power delivery and determine the delay and noise impact of
insufficient capacitance. Your supply will sag which will delay the output.
Add enough capacitance to achieve any critical IO timing you have. When you
model the on-die capacitor make sure you estimate the ESR of it. For that
matter make sure you properly model the ESL and ESR of all the components in
your power delivery network.
Depending on the IO and the speed you may find that on package capacitance
is needed because having PCB capacitance is not effective give the bandwidth
of you package. Make sure to run the simulations over multiple cycles to
observe any sagging that comes from insufficient capacitance at any point in
the delivery network. Don't just do one transition to determine the
capacitance!
At a 2 Gbps toggle rate there is no way the package will allow you to
recover with one cycle you will need enough capacitance to handle multiple
cycles of the data. Without an on-package capacitor you will need a huge on
die capacitor because the package bandwidth from PCB to die may achieve 150
- 250 MHz. The die to package substrate bandwidth can be higher which is why
on-package capacitance will help as well.
The issue with too much capacitance will be yield and leakage depending on
the process your in
Steve
p.s. also take a look at both more than one Voltage, process corner. Supply
voltage sage for a slow device may have more SSN induced delay than the fast
corner which will have more SSN. Make sure you look at both Noise and Delay
when evaluating decoupling.
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On
Behalf Of Lee Ritchey
Sent: Wednesday, April 09, 2008 2:12 PM
To: Chris Cheng; Stephane Tremblay; si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: On-die caps for IO supply
A common number I have seen used for 3.3V drivers is 100 pF per I/O. Seems
to work on many memory die. Simulation would determine if this is good
enough.
> [Original Message]
> From: Chris Cheng <Chris.Cheng@xxxxxxxx>
> To: Stephane Tremblay <strembl1@xxxxxxxxxx>; <si-list@xxxxxxxxxxxxx>
> Date: 4/9/2008 10:56:40 AM
> Subject: [SI-LIST] Re: On-die caps for IO supply
>
> I don't think you will like my answer but my experience is fill it up =
> with as much capacitor your technology people allow.
> If you are core limited, you are SOL to begin with.
> If you are pad limited, just fill the gap between the core and pad area =
> with decoupling cap before the yield police or the core power =
> distribution guy wants to take it for himself.
> It will take a lot more than "XXX from Si-list recommended this" to grow =
> your die to fit anything more than the above.
>
> -----Original Message-----
> From: si-list-bounce@xxxxxxxxxxxxx
> [mailto:si-list-bounce@xxxxxxxxxxxxx]On Behalf Of Stephane Tremblay
> Sent: Wednesday, April 09, 2008 7:33 AM
> To: si-list@xxxxxxxxxxxxx
> Cc: 'Stephane Tremblay'
> Subject: [SI-LIST] On-die caps for IO supply
>
>
> Hi SI-Listers,
> I am looking for a rule of thumb on the required on-die =
> capacitors needed for proper operation of a given IO (a DDR mem IO in my =
> case). I am looking for a number of "x" capacitance per IO.
>
> My IO can be programmed to 18 Ohms of drive and the measured slew-rate =
> is slightly higher than 6 V/ns for both rise and fall. The parasitic =
> capacitance of this IO is about 3.5 pF. The toggle rate could be as high =
> as 2 Gbps so I expect the IO rail to recover within reasonable limits =
> within half a period.
>
> I could always start by assuming the current I need just for the =
> transmission line (being a 50 Ohms one):
>
> dI/dt =3D 6 V/ns / 50 Ohms =3D 120 mA / ns (per IO)
>
> but this basic current demand calculation neglected the parasitic =
> capacitance of 3.5 pF.
>
> Some will say it is also greatly dependant of my power-gnd loop =
> inductance from IO to on-package decaps. On the other end, if my noise =
> spectrum is in the hundreds of MHz, I can't do much at the package level =
> to clean my die supply.
>
> So from your experience and knowledge, what would be a good start as a =
> required on-die capacitance required. I want to avoid my on-die IO rail =
> collapsing at a frequency that my package could not keep up.
>
> Thanks for the answers,
> Steph.
> =20
>
>
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