[SI-LIST] Re: On-die caps for IO supply
- From: "Kenneth W. Egan" <kegan@xxxxxxxxxxxxx>
- To: "'Chris Cheng'" <Chris.Cheng@xxxxxxxx>, <leeritchey@xxxxxxxxxxxxx>, "'Stephane Tremblay'" <strembl1@xxxxxxxxxx>, <si-list@xxxxxxxxxxxxx>
- Date: Wed, 9 Apr 2008 14:05:07 -0500
For UMC .18u standard CMOS technology, we've found that the device cap is
about 8.8ff/um^2. In .25u process its about 5-6ff/um^2.
100pF would then be about 11000um^2, assuming a .18um process node.
For 100+ channels this is 1million um^2. ( i.e. 1mm x 1mm die area just for
decoupling i/o)
Kenneth W. Egan
Chief Technology Officer
Vizionware, Inc.
12708 Riata Vista Circle, #A115
Austin, Texas 78727-7167
(512) 493-9660 (main)
(512) 493-9663 (direct)
(512) 470-7404 (cell)
(512) 493-9661 (fax)
kegan@xxxxxxxxxxxxxx
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On
Behalf Of Chris Cheng
Sent: Wednesday, April 09, 2008 1:28 PM
To: leeritchey@xxxxxxxxxxxxx; Stephane Tremblay; si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: On-die caps for IO supply
Do you have any idea how large an area 100pf will cost ? Do you have any =
idea how much yield impact it will do with a 100+ DDR channel I/O ?
-----Original Message-----
From: Lee Ritchey [mailto:leeritchey@xxxxxxxxxxxxx]
Sent: Wednesday, April 09, 2008 11:12 AM
To: Chris Cheng; Stephane Tremblay; si-list@xxxxxxxxxxxxx
Subject: RE: [SI-LIST] Re: On-die caps for IO supply
A common number I have seen used for 3.3V drivers is 100 pF per I/O. =
Seems
to work on many memory die. Simulation would determine if this is good
enough.
> [Original Message]
> From: Chris Cheng <Chris.Cheng@xxxxxxxx>
> To: Stephane Tremblay <strembl1@xxxxxxxxxx>; <si-list@xxxxxxxxxxxxx>
> Date: 4/9/2008 10:56:40 AM
> Subject: [SI-LIST] Re: On-die caps for IO supply =20
>
> I don't think you will like my answer but my experience is fill it up =
=3D
> with as much capacitor your technology people allow.
> If you are core limited, you are SOL to begin with.
> If you are pad limited, just fill the gap between the core and pad =
area =3D
> with decoupling cap before the yield police or the core power =3D
> distribution guy wants to take it for himself.
> It will take a lot more than "XXX from Si-list recommended this" to =
grow =3D
> your die to fit anything more than the above.
>
> -----Original Message-----
> From: si-list-bounce@xxxxxxxxxxxxx
> [mailto:si-list-bounce@xxxxxxxxxxxxx]On Behalf Of Stephane Tremblay
> Sent: Wednesday, April 09, 2008 7:33 AM
> To: si-list@xxxxxxxxxxxxx
> Cc: 'Stephane Tremblay'
> Subject: [SI-LIST] On-die caps for IO supply
>
>
> Hi SI-Listers,
> I am looking for a rule of thumb on the required on-die =3D
> capacitors needed for proper operation of a given IO (a DDR mem IO in =
my =3D
> case). I am looking for a number of "x" capacitance per IO.
>
> My IO can be programmed to 18 Ohms of drive and the measured slew-rate =
=3D
> is slightly higher than 6 V/ns for both rise and fall. The parasitic =
=3D
> capacitance of this IO is about 3.5 pF. The toggle rate could be as =
high =3D
> as 2 Gbps so I expect the IO rail to recover within reasonable limits =
=3D
> within half a period.
>
> I could always start by assuming the current I need just for the =3D
> transmission line (being a 50 Ohms one):
>
> dI/dt =3D3D 6 V/ns / 50 Ohms =3D3D 120 mA / ns (per IO)
>
> but this basic current demand calculation neglected the parasitic =3D
> capacitance of 3.5 pF.
>
> Some will say it is also greatly dependant of my power-gnd loop =3D
> inductance from IO to on-package decaps. On the other end, if my noise =
=3D
> spectrum is in the hundreds of MHz, I can't do much at the package =
level =3D
> to clean my die supply.
>
> So from your experience and knowledge, what would be a good start as =
a =3D
> required on-die capacitance required. I want to avoid my on-die IO =
rail =3D
> collapsing at a frequency that my package could not keep up.
>
> Thanks for the answers,
> Steph.
> =3D20
>
>
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