[SI-LIST] Re: EMC
- From: Dave Barr <Dbarr@xxxxxxxxxxxxx>
- To: clandrum@xxxxxxxxx
- Date: Thu, 06 Nov 2003 10:54:28 -0800
Chris,
Howard Johnson's website has an article about using bypass capacitors above
their resonant frequency. -Dave Barr
Chris Landrum x311 wrote:
> This is interesting. Can you dig up the paper?
> -----Original Message-----
> From: Bart Bouma [mailto:bart.bouma@xxxxxxxxx]
> Sent: Thursday, November 06, 2003 2:45 AM
> To: clandrum@xxxxxxxxx
> Cc: 'chris.mcgrath@xxxxxxxx'; si-list@xxxxxxxxxxxxx;
> si-list-bounce@xxxxxxxxxxxxx
> Subject: Re: [SI-LIST] Re: EMC
>
> Hi Chris,
>
> capacitance would be some tens of nF for the mentioned board, but indeed
> with very low inductance.
> So rather small, but, and I think you will agree, it will be quite effective
> at frequencies in the GHz range.
>
> I have to disagree with you on that an Inductive Capacitor will be useless
> for decoupling.
> A capacitor that has gone inductive can still provide a low impedance:
> somewhere (a paper from SUN?) I saw the definition 'decoupling inductor'.
> Normally, a decoupling capacitor is USED AROUND its self resonant frequency,
> using the low impedance region around this 'notch'.
> So using both the capacitive part and the inductive part of the impedance
> plot.
> As long it's impedance is below a certain target level, say 100milli Ohm, it
> is still usable for decoupling.
>
> kind regards, Bart Bouma
> www.yageo.com
>
> Chris Landrum x311 <clandrum@xxxxxxxxx>
>
> 05-11-03 15:58
> Sent by: si-list-bounce@xxxxxxxxxxxxx
>
> Please respond to clandrum
>
>
> To: "'chris.mcgrath@xxxxxxxx'" <chris.mcgrath@xxxxxxxx>
> cc: si-list@xxxxxxxxxxxxx
> Subject: [SI-LIST] Re: EMC
> Category:
>
> You are correct is noticing the capacitance is small.... But don't forget,
> you are getting rid of much of the parasitic inductance that will cause
> resonance, as compared to an SMT or leaded cap. This parasitic inductance
> effectively causes your bypass cap to be AN INDUCTOR at any freq above
> 100MHz!!! In other words it is USELESS to your power sub-system. You might
> as well have not used it at all and saved your company the $0.001/brd. With
> the inner planer capacitor, it is much more effective at high frequency,
> albeit, it does not provide a lot of charge. It can make all the difference
> in the world at higher freq.
>
> -----Original Message-----
> From: Chris McGrath [mailto:chris.mcgrath@xxxxxxxx]
> Sent: Wednesday, November 05, 2003 9:43 AM
> Cc: si-list@xxxxxxxxxxxxx
> Subject: [SI-LIST] Re: EMC
>
> Given, say, a 10"x10" board with 5 mil dielectrics, the capacitance due
> to the ground fills would be extremely small, wouldn't they? =20
>
> I don't disagree that the fill method has less inductance, but I think
> that it would have little effective capacitance that would have a
> substantial impact on decoupling the devices due to the small copper
> area and the distance to the dielectric. From your description of the
> issue, it sounds like ground filling would be pretty far down the list
> of the EMI designer's bag of tricks.
>
> -Chris
>
> > -----Original Message-----
> > From: Chris Landrum x311 [mailto:clandrum@xxxxxxxxx]=20
> > Sent: Wednesday, November 05, 2003 9:16 AM
> > To: Chris McGrath
> > Cc: si-list@xxxxxxxxxxxxx
> > Subject: RE: [SI-LIST] Re: EMC
> >=20
> >=20
> > Ground filling is useful to create inner layer capacitance=20
> > for the power sub-system of the PCB. By filling GND on a=20
> > signal layer that is directly adjacent to a PWR plane a=20
> > capacitor will be created. This capacitor is often times=20
> > MUCH more effective at providing energy to components because=20
> > it is far less inductive than a normal leaded or chip capacitor. =20
> >=20
> > EMI can be caused by an improperly designed power sub-system.=20
> > What can happen here is current gradients can be formed in=20
> > the PWR/GND planes that can effectively cause radiation=20
> > assuming there is an antenna nearby. Also of concern is VCC=20
> > and GND bounce. The plane capacitors formed can help avoid=20
> > this problem.
> >=20
> > By ensuring that the chips are getting the proper energy such=20
> > that VCC and GND bounce do not occur, you are thereby=20
> > reducing the probability that EMI problems can be caused by=20
> > the power sub-system.
> >=20
> > -----Original Message-----
> > From: Chris McGrath [mailto:chris.mcgrath@xxxxxxxx]
> > Sent: Wednesday, November 05, 2003 8:35 AM
> > Cc: si-list@xxxxxxxxxxxxx
> > Subject: [SI-LIST] Re: EMC
> >=20
> >=20
> > The "ground filling" is a topic that has been discussed at my=20
> > company recently and I wanted to get the list's feedback on=20
> > why this is done. We never do ground filling on any layers=20
> > and the only reason that I have ever heard for it was to=20
> > reduce EMI, but given the disadvantages (increased thermal=20
> > profile, potential for crosstalk, PCB viewer and gerber=20
> > viewer complications, etc.) and the fact that I have never=20
> > been able to find data or any science to back up the EMI=20
> > argument, I don't see any benefit to ground filling on signal=20
> > layers. (Of note is that by using the term "ground filling",=20
> > I am not referring to "thieving" to equalize the copper=20
> > distribution to facilitate PCB fabrication.)
> >=20
> > I am very interested in hearing feedback from any of you.
> >=20
> > -Chris
> >=20
> >=20
> > > -----Original Message-----
> > > From: Suresh.K [mailto:sureshk@xxxxxxxxxxxxxx]=3D20
> > > Sent: Wednesday, November 05, 2003 2:54 AM
> > > To: subramani
> > > Cc: si-list@xxxxxxxxxxxxx
> > > Subject: [SI-LIST] Re: EMC
> > >=3D20
> > >=3D20
> > >=3D20
> > > Dear Sir,
> > >=3D20
> > > According to your Board Stack you have two strip lines and=3D20 one =
>
> > >assymmetrical dual stripline,but the two strip lines are=3D20 =20
> > bounded by=20
> > >one side power plane and Ground Plane on the other=3D20 side......
> > >=3D20
> > > If you have both side ground plane reference for the strip=3D20
> > > lines ,you can route all the Impedance controlled signals on=3D20
> > > Layer2 & layer8,because strip lines bounded by ground planes=3D20
> > > will be best layer for better signal=3D20
> > > integrity.
> > >=3D20
> > > But now you have assymmetrical dual stripline bounded by=3D20
> > > ground planes,so I beleive that layer 5&6 may be better=3D20
> > > option for routing clock signals,which will useful for return=3D20
> > > path, but you need to care of tandem=3D20
> > > pair of traces.
> > >=3D20
> > > and regarding board power plane EMI,you can follow 20H rule=3D20
> > > on layer2& layer9 power planes to reduce the power plane EMI=3D20
> > > and Top & Bottom layers you are doing Ground fill, so I think=3D20
> > > the device EMI will be controlled by the Ground fills.
> > >=3D20
> > > Regards,
> > > Suresh.K,
> > > Vth EDA Lab,
> > > C-DOT,
> > > Bangalore-52.
> > >=3D20
> > >=3D20
> > >=3D20
> > >=3D20
> > >=3D20
> > > On Wed, 5 Nov 2003, subramani wrote:
> > >=3D20
> > > > Hello,
> > > >=3D20
> > > > I am doing a board design. It has to pass stringent EMI tests. =
> =3D20
> > > > Mine is a 10 layer board.
> > > >=3D20
> > > > The board stack up is
> > > > 1 TOP component, GND filling
> > > > 2 Power
> > > > 3 signal
> > > > 4 GND filling
> > > > 5 signal
> > > > 6 Signal
> > > > 7 GND filling
> > > > 8 Signal
> > > > 9 Power
> > > > 10 Bottom Component, GND filling
> > > >=3D20
> > > > The board has SDRAM operating at 100Mhz. Where should I=20
> > route the=3D20
> > > > clocks. Could anyone tell me about the ways and means of=3D20
> > > reducing EMI.=3D20
> > > > The SDRAM is placed that is near to the edge of PCB. Will it=20
> > > >cause=3D20 radiation. Is there a formula for keepout distance. =
> =3D20
> > > > Regards
> > > > Subramani
> > > > Mistral
> > > >=3D20
> > > >=3D20
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