[SI-LIST] EMC
- From: Chris Landrum x311 <clandrum@xxxxxxxxx>
- To: "'si-list@xxxxxxxxxxxxx'" <si-list@xxxxxxxxxxxxx>
- Date: Wed, 5 Nov 2003 08:56:05 -0500
I would disagree with the statement that SI is better on stripline layers
that are between two GROUND planes. A stripline will behave just as well
between ANY plane (be it GND or PWR) as long as the two planes are AC
coupled. If the power subsystem is designed correctly, the PWR and GND
planes will effectively be shorted together at AC by the decoupling/bypass
caps that are on the board. Thus, there is no reason to make sure your
stripline's are sandwhiched between two GND planes. What is more important
for transmission line impedance AND for EMI is that the power sub-system is
designed correctly. Your power subsytem should be LOW (mOhm)impedance
through the frequencies of interest. This can be accomplished by good
stack-up design using plane capacitors (PWR and GND planes adjacent to
eachother) and by using the RIGHT kind of decoupling caps.
The clocks are not the only signals you should worry about for EMI. ANY
signals that have fast rise/fall times should be considered critical. From
an EMI standpoint, all of these signals are better off between two plane
layers. Keeping the signals away from the edge of the board may help as
well. Lastly, whatever enclosure is used to house your board should be
designed to contain EMI radiation. Also remember, that an enclosure that is
good at keeping radiation in is also good at keeping radiation out which is
a necessary to pass UL immunity tests.
Lastly, the SDRAMS at the edsge should not pose a problem as long as the
rest of the system is appropriately designed. I am also assuming that the
SDRAM manufacturer has done their part and properly designed the SDRAM
package.
I hope this helps.
Chris
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