[SI-LIST] Re: EMC
- From: "Chris McGrath" <chris.mcgrath@xxxxxxxx>
- Date: Wed, 5 Nov 2003 05:35:14 -0800
The "ground filling" is a topic that has been discussed at my company
recently and I wanted to get the list's feedback on why this is done.
We never do ground filling on any layers and the only reason that I have
ever heard for it was to reduce EMI, but given the disadvantages
(increased thermal profile, potential for crosstalk, PCB viewer and
gerber viewer complications, etc.) and the fact that I have never been
able to find data or any science to back up the EMI argument, I don't
see any benefit to ground filling on signal layers. (Of note is that by
using the term "ground filling", I am not referring to "thieving" to
equalize the copper distribution to facilitate PCB fabrication.)
I am very interested in hearing feedback from any of you.
-Chris
> -----Original Message-----
> From: Suresh.K [mailto:sureshk@xxxxxxxxxxxxxx]=20
> Sent: Wednesday, November 05, 2003 2:54 AM
> To: subramani
> Cc: si-list@xxxxxxxxxxxxx
> Subject: [SI-LIST] Re: EMC
>=20
>=20
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> Dear Sir,
>=20
> According to your Board Stack you have two strip lines and=20
> one assymmetrical dual stripline,but the two strip lines are=20
> bounded by one side power plane and Ground Plane on the other=20
> side......
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> If you have both side ground plane reference for the strip=20
> lines ,you can route all the Impedance controlled signals on=20
> Layer2 & layer8,because strip lines bounded by ground planes=20
> will be best layer for better signal=20
> integrity.
>=20
> But now you have assymmetrical dual stripline bounded by=20
> ground planes,so I beleive that layer 5&6 may be better=20
> option for routing clock signals,which will useful for return=20
> path, but you need to care of tandem=20
> pair of traces.
>=20
> and regarding board power plane EMI,you can follow 20H rule=20
> on layer2& layer9 power planes to reduce the power plane EMI=20
> and Top & Bottom layers you are doing Ground fill, so I think=20
> the device EMI will be controlled by the Ground fills.
>=20
> Regards,
> Suresh.K,
> Vth EDA Lab,
> C-DOT,
> Bangalore-52.
>=20
>=20
>=20
>=20
>=20
> On Wed, 5 Nov 2003, subramani wrote:
>=20
> > Hello,
> >=20
> > I am doing a board design. It has to pass stringent EMI tests.
> >=20
> > Mine is a 10 layer board.
> >=20
> > The board stack up is
> > 1 TOP component, GND filling
> > 2 Power
> > 3 signal
> > 4 GND filling
> > 5 signal
> > 6 Signal
> > 7 GND filling
> > 8 Signal
> > 9 Power
> > 10 Bottom Component, GND filling
> >=20
> > The board has SDRAM operating at 100Mhz. Where should I route the=20
> > clocks. Could anyone tell me about the ways and means of=20
> reducing EMI.=20
> > The SDRAM is placed that is near to the edge of PCB. Will it cause=20
> > radiation. Is there a formula for keepout distance.
> >=20
> > Regards
> > Subramani
> > Mistral
> >=20
> >=20
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