[SI-LIST] Re: Do you really ship products at BER 10e-xx ?
- From: "Alfred P. Neves" <al.neves@xxxxxxxxxxx>
- To: <si-list@xxxxxxxxxxxxx>
- Date: Mon, 18 Apr 2005 16:20:04 -0700
Chris,
Good point regarding the distinction between extrinsic versus intrinsic
jitter of a PLL. This thread has helped me better understand the issues
of system design versus the issues of generating a PLL with very low
intrinsic phase jitter. A lot of my experience has been in making good
PLL's and CDR's where extrinsic jitter from the power supply, power
plane resonance and junk coupling into the loop filter is analyzed from
a characterization perspective.
When we had to optimize the loop characteristics for PLL's an overriding
consideration has been the conflicting requirements of low jitter
generation (GR-253, Sonet) and jitter transfer. If you make the loop BW
large, and the loop gain high you often have poor loop stability of
phase/frequency, such that you reject intrinsic VCO noise, but have poor
jitter transfer performance. Remember that there are parasitics in the
loop and they cause peaking in the loop response, along with higher
order poles in VCO, so when the loop BW increases loop stability may
suffer. Verify that the equations are correct (they are usually fairly
lousy linearized approximations of a charge-pump sampling system)and the
loop is set correctly, we can check the loop dynamics with Spectrum
Analyzer and autocorrelation analysis often using Wavecrest instruments.
Scott McMorrow raised an important point is that if you characterize
your PLL's correctly you can specifically target range of frequencies
for power plane resonance, supply issues, etc., that the PLL will be
most sensitive. You would do this by using your 3D solver to optimize
the system performance of the physical platform, separate from the IC's
RJ and tolerance issues.
Three good references:
1. "Analysis of Jitter due to Power-Supply Noise in Phase Locked
Loops", Hedar, Pedram, IEEE 2000 CICC 2. "Jitter in Ring Oscillators",
John A. McNeill, ISCC vol 32, no 6 1997 3. Phase Locked Loops for
High-Frequency Receivers and Transmittters- Part1 and 2, Analog Dialogue
33-3(1999)
I have a list of other really good jitter references, I can send them to
you offline.
Alfred P. Neves
Teraspeed Consulting Group LLC
121 North River Drive
Narragansett, RI 02882
Hillsboro Office
735 SE 16th Ave.
Hillsboro, OR, 97123
(503) 679 2429 Voice
(503) 210 7727 Fax
Main office
(401) 284-1827 Business
(401) 284-1840 Fax
http://www.teraspeed.com
Teraspeed is the registered service mark
of Teraspeed Consulting Group LLC
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
On Behalf Of Chris Cheng
Sent: Monday, April 18, 2005 2:46 PM
Cc: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: Do you really ship products at BER 10e-xx ?
My PLL design is getting rusty so if I am mumbling nonsense please
correct me. If you are dealing with classical PLL design, the loop
filter is always a trade-off between the high pass VCO phase noise and
the low pass input phase noise. My money is always on the VCO phase
noise and I optimize it for such. Afterall, if I read Geogre's response
in the same thread, "But if you solve all these problems to the extent
that there is sufficient eye-opening inside the receiver, then you are
dealing with errors caused by the second-order effects, mainly the RJ
from TX PLL, RX PLL / CDR circuits." That's sounds like a controlled
input phase noise (good eye opening) vs. a out of control VCO phase
noise problem (you have non-zero BER). And that's why our employers pay
us peanuts to design a power distribution that ensure no "large supply
glitches" or at least some good PLLVDD filters to avoid that to happen,
right ?
As to making sure the loop filter damping factor, one can either observe
directly the VCO control voltage or monitor the VCO output frequency in
the modulation domain during a cold start to deduce the stability
factor, there is no magic about it. You either get it right or you are
back to the drawing board. There is no 10e-xx probably you are either
right or wrong. And if you are talking about these bang bang PLL's.
AFAIK, if you are operating under the slew rate limit, your hunting
jitter is bounded and is related to the metastability limit of the FF
you use. And they have the added bonus of even if the input phase noise
is large, they are limited by Jwalk which is sqrt of input jitter. I
can't argue that a 1ps rms xtalk MAY have a 100ps jitter within the life
time of the universe but it is hard to extend that to say a properly
design system is one big 10-exx distribution.
-----Original Message-----
From: Alfred P. Neves [mailto:al.neves@xxxxxxxxxxx]
Sent: Monday, April 18, 2005 9:31 AM
To: weirsi@xxxxxxxxxx; andyp@xxxxxxxxxxxxxxxxxxxxxx;
Bradley.S.Henson@xxxxxxxxxx
Cc: Chris.Cheng@xxxxxxxxxxxx; si-list@xxxxxxxxxxxxx
Subject: RE: [SI-LIST] Re: Do you really ship products at BER 10e-xx ?
Steve,
For PLL's that blow lock occasionally, have found the following problems
- large supply glitches, large modulations of the input (most often
periodic), and more importantly improperly designed PLL loop filter
and/or the VCO delay does not correspond to the operating Fout/Fin of
the PLL.
When the VCO and the loop is not designed or optimized correctly, it
becomes very apparent when analyzing the phase noise with Spectrum
analyzer. John McNeill also wrote numerous articles on autocorrelation
analysis that also provides some simple an obvious measures of PLL loop
dynamics that neatly correspond to Spectrum analysis (Wavecrest
developed this further, Mike Li)- we are using these methods for
analysis of loop dynamics, especially for downstream PLL's possibly
impacted by jitter multiplication. Wrong Fin shows up as a loop dynamic
issue since the VCO doesn't have adequate K factor (radians/volt) and
the loop is not designed correctly so you have peaking in the loop or
the loop has inadequate gain so you don't reject enough VCO phase noise.
I really like this approach since you can tie the SSO, plane resonance,
PLL loop dynamics, and switching power supply junk with jitter analysis
of the PLL.
Where Fin does not change or intitialize in a training sequence, and the
PLL exhibits low jitter (consistent with the VCO noise and Fin phase
noise) have not found lock problems - anyone else have different
experience than this???
Alfred P. Neves
Teraspeed Consulting Group LLC
121 North River Drive
Narragansett, RI 02882
Hillsboro Office
735 SE 16th Ave.
Hillsboro, OR, 97123
(503) 679 2429 Voice
(503) 210 7727 Fax
Main office
(401) 284-1827 Business
(401) 284-1840 Fax
http://www.teraspeed.com
Teraspeed is the registered service mark
of Teraspeed Consulting Group LLC
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
On Behalf Of steve weir
Sent: Monday, April 18, 2005 4:31 AM
To: andyp@xxxxxxxxxxxxxxxxxxxxxx; Bradley.S.Henson@xxxxxxxxxx
Cc: Chris.Cheng@xxxxxxxxxxxx; si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: Do you really ship products at BER 10e-xx ?
Andy, three issues:
1) Know / control the environment. PLL's don't just fall out of lock by
themselves without help from the outside, power disturbance, being the
number one culprit. If you insure that power is clean and undisturbed
by
things like digital return currents, a properly designed PLL will not
lose
lock. Similarly, your cabling will be subejected to whatever ESD and
EFT
is in the environment.
2) All data links eventually get errors. It is a matter of time. If
bad
things will happen as a result of a communication link error or failure
then you need some sort of back-up.
3) Large interleaving ratios can help reduce the probability that a run
of
errors will be uncorrectable.
Steve
At 03:35 PM 4/12/2005 -0700, Andy Pedler wrote:
>This is actually right-on topic with a design problem that I'm
>investigating. Here's what I require, and maybe someone can suggest
>something.
>
>I need a relatively high-speed serial link; let's say 1 Gbps, but if I
>can run 2.5 Gbps it will save me cost in another part of the design.
>I'd like to run over a backplane, but the design may simply be
>board-to-board connectors. It could also be 1-2 foot cables (perhaps
>Infiniband type cables). It's a theoretical exercise at this point.
>But I can certainly live with 1 Gbps. I can add forward error
>correction into my data that is traversing this link, so I can live
>with an occasional *single* bit error that comes along once in a blue
>moon. But my system will crash and burn if the receiver ever gets a
>continuous stream of errors. So I would be happy with a predictable
>BER of even 1E-7 or 1E-9, so long as the errors are single bit and
>correctable. But even 1E-20 is bad if the errors show up in huge
>numbers all at once.
>
>When I've talked to serdes vendors about how they define BER, I've been
>told that these serial links typically operate error free, but every so
>often for whatever reason (Chris's cosmic ray), a PLL might get just
>out of sync and have to re-lock, and when that happens you get a ton of
>errors all at once. Obviously, that will kill my system.
>
>I've built chassis systems with 1 Gbps backplanes and run them for
>weeks at a time without recording any errors. But that still doesn't
>make me extremely confident that I would *never* see a problem. This
>system would have to run for months at a time, and a hiccup would cause
>a lot of problems.
>
>Any thoughts?
>
>Andy Pedler - Greenfield Networks
>
>
>
>
>
>Henson, Bradley S wrote:
>
> > This could make an interesting topic. I have to say that in general,
> > I have noticed the same trend: Links work so well the BER is hard to
> > determine (lots of test time or link-stress)-or- the links are
> > totally messed up. However, I did get called in to troubleshoot a
> > Fibre channel application that was just marginal on some of the
> > links. By that I mean they would almost make the spec 1E-12 BER
> > sometimes, but usually fell short. Some days they operated
> > considerably poorer than 1E-12, but not pure garbage.=20
> >
>
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