[SI-LIST] Re: Do you really ship products at BER 10e-xx ?
- From: steve weir <weirsi@xxxxxxxxxx>
- To: cshroff@xxxxxxxxx, <ray.anderson@xxxxxxxxxx>, <Bradley.S.Henson@xxxxxxxxxx>
- Date: Wed, 13 Apr 2005 08:19:11 -0700
Chirag from the data that Ihave seen ( available from Xilinx ) they do get
SEU's at low rates. the consequence of an SEU in an FPGA configuration bit
is pretty insidious. It alters the function until the code is
reloaded. Detection sould be very difficult. Sparsely coded FSM's could
be particularly troublesome.
Steve
At 11:08 AM 4/13/2005 -0400, Chirag Shroff (cshroff) wrote:
>=20
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> Our SEU research group has several test sites co-located at a number
>of high-altitude astronomical observatory mountain top locations.
>
>So do you see Soft error events on these test sites ?
>
>- --Chirag Shroff
>
> =20
>
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