Stefan exactly! The oppressively competitive computer market has forced Intel to design for total system cost. It's a lesson that many other chip builders need to learn well if they expect to succeed in a market that is becoming more consumer electronic, sic low total cost, oriented. Regards, Steve. At 06:27 PM 5/17/2005 +0200, Stefan Ludwig wrote: >A slightly different angle on this is the following: > >Intel's 90nm processors consume 130W these days (desktop and server >parts). That can be more than 100 Amps! You simply can't afford a "cheap", >"un-bypassed" package with this sort of power and current requirements. >Once you bypass to the max on the die itself and in the package, you end >up with a lot less stringent requirements on the PCB. > >A nice side effect of the above and a requirement from Intel's customers >is that their processors need to run with the cheapest possible boards >produced by the customers' contract manufacturers. Intel must engineer a >rock solid chip/package solution, which then allows their customers to >have a simpler board structure and cheaper bypassing. For a while, Intel >delivered their processors in the form of cartridges, so that even the >least capable customer can build a PC board that still works. It had the >processor die and cache SRAMs on it, as well as lots of bypass caps. > >Nowadays, they sell you boxed chips, with the heat sink and cooling fan, >so you don't blow up "your precious!" > >Stefan > >"May you live in interesting times!" - Chinese curse (<- NOT, as it turns >out if you google for it.) > >steve weir wrote: > >>Ken, >> >>Thanks. >> >>It is precisely because Lindenhurst has a relatively high spreading >>inductance for power that I think people need to pay close attention to >>it. Carpet bombing that sort of board with bypass caps is futile, and >>because of the amount of bypass included in the processors, >>unnecessary. Now, you may have other chips on your board that impose >>that cost of extra and thin layers close to the IC mounting surface, but >>as Lindenhurst demonstrates, with proper engineering of the chip / >>package, that expense is not mandatory. >> >>Regards, >> >>Steve. >> >>At 09:25 AM 5/17/2005 -0600, Ken Cantrell wrote: >> >> >>>Steve, >>>"do you develop it with geographically specific transfer impedances to each >>>IC >>>attachment or do you globalize?" - geographically specific transfer >>>impedances. >>>"Do you develop an independent impedance versus frequency for each big chip, >>>or do you use the worst case device?" - independent impedance versus >>>frequency. >>>However, I sometimes globalize in the sense that I place some of the >>>capacitance(mid-to-high)near the chips and some of the capacitance in an >>>inter-chip grid,being careful about lambda/4 placement. It just depends on >>>the situation. >>> >>>I had looked at the Lindenhurst material some time ago, and frankly, didn't >>>get as much out of it as you. I thought that the basic stack-up was OK, but >>>could be improved on for my situation. I prefer to have tight power/ground >>>coupling, as close to the chip as possible, even if it means a two layer >>>hit. But that's the nice thing about the list, exposure to other view >>>points; someone else seeing something that you missed. I will review. >>> >>>Thanks, >>>Ken >>> >>> >>>-----Original Message----- >>>From: steve weir [mailto:weirsi@xxxxxxxxxx] >>>Sent: Monday, May 16, 2005 5:34 PM >>>To: Ken Cantrell; Ken Cantrell; Larry.Smith@xxxxxxx >>>Cc: joepaul@xxxxxxxxxxx; si-list@xxxxxxxxxxxxx >>>Subject: RE: [SI-LIST] Re: Decoupling capacitors >>> >>> >>>Ken, if Larry's F^N method meets your specifications then you are all >>>set. There is no question that it does what is claimed which is yield a >>>relatively flat impedance profile with a higher ESR than a big "V" with the >>>same reject band end-point insertion loss. >>> >>>The real key in all of this is as Istvan noted the specifications. It also >>>turns-out that the inductance in both the components and the mounting >>>structure remains the enemy. Even more so for "capacitors by the decade" >>>than the other two methods. This raises an interesting issue, because if >>>one wants to drive down the real-estate as a primary goal, the two >>>available choices are IDC and X2Y >>> >>>If you don't mind my asking, when you develop you specification, do you >>>develop it with geographically specific transfer impedances to each IC >>>attachment or do you globalize? Do you develop an independent impedance >>>versus frequency for each big chip, or do you use the worst case device? >>> >>>Lindenhurst is the current example that I am referring to. Search Intel >>>for DDR2 and it should come up. If you can't find it, I will send you a >>>copy. Lindenhurst is a great example of how good engineering was used to >>>yield high quality, and low-cost: >>> >>>8 layers, 2 power, 2 logic common and 4 signal. All signal layers strongly >>>reference logic common. Cavity resonance and issues of switching return >>>layers are minimized. The two power layers are relatively far from the >>>logic common layers, about 15 mils for a net effective of about 7mils, but >>>with the nearest power layer to the IC over 25 mils down the stack. >>> >>>What, 7 mils effective. that's 35pH, or some 22mohms at 100MHz? How can >>>that be? What happened to a milliohm at 100MHz? How can Intel be off by >>>more than an order of magnitude and still make servers that run >>>non-stop? Hasn't it been drilled into everyone's head that we are supposed >>>to need multiple pairs of power / common with thin dielectric right up >>>against the IC to meet these "modern requirements"? >>> >>>Well, those smart people in Santa Clara apparently missed the class where >>>we were all "taught" these truisms. Instead they got the funny idea that >>>big structures make for big HF losses and they should move the HF storage >>>into the package and drop the definition of HF for power delivery, and >>>therefore the package / internal storage cut-off frequency way, way >>>down. The result is dramatic system savings over the ever more futile >>>efforts to try and jam many amperes at high frequency through local board >>>interconnect and into a package. The only way to save even more ( and it >>>is MANY millions more each year ) money is to make the in-package >>>capacitors X2Ys. I believe it was Scott in a comment to Chris who once >>>noted that a well designed package does not demand much from the PCB. >>> >>>There is a lot to be learned from these very shrewd decisions by >>>Intel. Alas for the other chips we buy, our other vendors may not be so >>>forward thinking and impose on us expensive PCB level solutions. >>> >>>Regards, >>> >>> >>>Steve >>> >>> >>>At 04:27 PM 5/16/2005 -0600, Ken Cantrell wrote: >>> >>> >>>>Steve, >>>>I guess I'm partial to Larry's method because I'm in HPC and have "insanely >>>>low PDS requirements" also. I could argue about "higher inductance with a >>>>reduced count" between big V and fine multi-pole being as big of an issue >>>> >>>as >>> >>> >>>>you are implying, but that is a topic in itself. I have found that a good >>>>board layout eliminates most of the issues (whatever they are), just as >>>>theory overestimates the severity of most problems. I will review your >>>>material (didn't mean to make it seem so black and white, know it isn't), >>>>and am looking forward to your paper as stated in my response to Istvan. >>>>On the Intel 8 layer server stack-up, are you talking about the Lindenhurst >>>>board stack-up? Do you have a pointer handy? >>>>Thanks, >>>>Ken >>>> >>>>-----Original Message----- >>>>From: steve weir [mailto:weirsi@xxxxxxxxxx] >>>>Sent: Monday, May 16, 2005 3:45 PM >>>>To: Ken Cantrell; Larry.Smith@xxxxxxx >>>>Cc: joepaul@xxxxxxxxxxx; si-list@xxxxxxxxxxxxx >>>>Subject: RE: [SI-LIST] Re: Decoupling capacitors >>>> >>>> >>>>Ken, please see also my comments to Larry. Please do review, because it is >>>>not as nearly black and white as you think. The price for reduced >>>>capacitor count is a higher inductance in the capacitor network. Do we >>>>care? Well that all depends on how sharp and uniform a cut-off one >>>>presumes for the IC packages. ( Assuming of course we are using bypass >>>>capacitors to bypass power and not signals. ) If that cut-off is not sharp >>>>or uniform, then at the end of the day equal inductance is what we seek and >>>>the quantity advantage of the fine multipole evaporates. If one makes what >>>>I consider a mistake, but is still done, of relying on the power bypass >>>>network for signal return, then the bypass network is further enlisted to >>>>support much higher frequencies. This is I feel very good at one >>>>thing: making assemblies more expensive. >>>> >>>>In my highly opinionated view, the Intel 8 layer server stack-up should be >>>>the basis of a required one or two week course for all SI and PI >>>>engineers. Big "V" works great on those boards designed and built to very, >>>>very demanding cost targets, while supporting behemoth processors and big >>>>fast front-side busses. It is a shining example of using the principles >>>>that experts like Chris have been driving home here for a long time. >>>> >>>>Big "V" is not without its limitations. Neither is fine multipole. In the >>>>hands of an experienced engineer, each can be used effectively. Fine >>>>multipole or what I prefer to call F^N was developed by smart people at Sun >>>>to solve a problem and they succeeded. It just doesn't make it the only >>>>viable solution. >>>> >>>>Regards, >>>> >>>> >>>>Steve. >>>>At 11:21 AM 5/16/2005 -0600, Ken Cantrell wrote: >>>> >>>> >>>>>Gosh - >>>>>"In many common cases, it is just a rote practice that provides no >>>>>actual value. Life with SMT devices is much different today than when we >>>>>had leaded devices and those practices were first adopted." >>>>>I know this has been a long, ongoing issue, and I've read the majority of >>>>>Steve's and Istvan's material. Maybe I need to review. However, if you >>>>>take any Zo vs Frequency (100KHz to 100MHz)profile with a target >>>>> >>>impedance, >>> >>> >>>>>and plot big V vs Larry's method, you always end up with fewer caps with >>>>>Larry's method, and it's more like a 20% to 30% reduction in count over >>>>> >>>big >>> >>> >>>>>V. And you don't have any abrupt impedance changes at the ends, just a >>>>> >>>>bunch >>>> >>>> >>>>>of little cycloids that are near or at the target impedance line. At >>>>> >>>>least >>>> >>>> >>>>>that's what my handy-dandy copy of D. Brooks' Bypass Impedance Calculator >>>>>shows. >>>>>The real issue, at least for me, is what Larry states below about low and >>>>>high fequency anti-resonances. How do you, Steve/Howard/Istvan, address >>>>>this? >>>>> >>>>>Not a big fan of big V, >>>>> >>>>>Ken >>>>> >>>>> >>>>>-----Original Message----- >>>>>From: si-list-bounce@xxxxxxxxxxxxx >>>>>[mailto:si-list-bounce@xxxxxxxxxxxxx]On Behalf Of Larry SMITH >>>>>Sent: Monday, May 16, 2005 10:14 AM >>>>>To: weirsi@xxxxxxxxxx >>>>>Cc: joepaul@xxxxxxxxxxx; si-list@xxxxxxxxxxxxx >>>>>Subject: [SI-LIST] Re: Decoupling capacitors >>>>> >>>>> >>>>>Steve - The "big V" approach makes a very low impedance at the series >>>>>resonant frequency of the capacitor chosen. With this method, problems >>>>>can arise about a decade above and below the SRF where the decoupling >>>>>capacitors have to interface with other components in the system. >>>>> >>>>>On the low frequency side, the output of the VRM is inductive. It's >>>>>impedance crosses the capacitive impedance of all the big V caps in >>>>>parallel and usually makes a fairly high Q resonant peak in the kHz or >>>>>low MHz region. >>>>> >>>>>On the other end of the spectrum, the inductance of all the caps in >>>>>parallel usually resonates with the capacitance of the power planes and >>>>>make a high Q resonant peak in the 100MHz region. These are the two >>>>>"gotcha's" associated with the big V method. "Antiresonant" peaks at >>>>>any frequecy can (and often does) cause trouble in power distribution >>>>>systems. >>>>> >>>>>You can add additional capacitor values to address the newly created >>>>>peaks, but then you end up with more peaks.. If you add enough >>>>>capacitor values to eliminate all the peaks, you end up with a flat >>>>>frequency profile. This is the one I like. >>>>> >>>>>regards, >>>>>Larry Smith >>>>>Sun Microsystems >>>>> >>>>>steve weir wrote: >>>>> >>>>> >>>>>>Joe Paul, the ESL may be the same but the ESR of the 1uF in the same >>>>>>chemistry and voltage will definitely be about 35-40% that of the >>>>>>0.1uF. It is very unlikely that 0.1uF will provide any cost or >>>>>> >>>>>performance >>>>> >>>>> >>>>>>advantage over 1uF in the same 0603 case from the same mfg at a low >>>>>> >>>>>voltage >>>>> >>>>> >>>>>>rating. Due to cover layer considerations, depending on the voltage >>>>>> >>>and >>> >>> >>>>>>chemistry, the 1uF may actually exhibit lower mounted inductance than >>>>>> >>>>the >>>> >>>> >>>>>0.1uF >>>>> >>>>> >>>>>>At 2ns/ 160MHz, both capacitors are fully inductive and cover layer >>>>>> >>>>issues >>>> >>>> >>>>>>aside will have very similar performance. The 1.0uF capacitor has the >>>>>>benefit of more capacitance which generally makes it easier to >>>>>> >>>stabilize >>> >>> >>>>>>the transition from the bulk capacitors / VRM. Fans of the big "V" >>>>>> >>>like >>> >>> >>>>>>Dr. Johnson, Istvan Novak, and myself will usually advise that at the >>>>>> >>>>>same: >>>>> >>>>> >>>>>>cost, package size and chemistry, take the bigger capacitor. If you >>>>>> >>>>want >>>> >>>> >>>>>>to find out why some people do things differently, take a look at >>>>>> >>>Larry >>> >>> >>>>>>Smith and company's papers on multipole capacitor networks. If >>>>>> >>>nothing >>> >>> >>>>>>else, those papers should help you better understand what you are >>>>>> >>>doing >>> >>> >>>>>>whether or not you elect to follow the methods they describe. >>>>>> >>>>>>If you really want to see how your capacitors perform and have access >>>>>> >>>to >>> >>> >>>>a >>>> >>>> >>>>>>VNA, I suggest building a test board. You can get details on such a >>>>>> >>>>board >>>> >>>> >>>>>>from Istvan's papers on his web site, or from mine on the X2Y web >>>>>>site. You can put together a decent set of CPW test fixtures for >>>>>> >>>under >>> >>> >>>>>>$200. cash and some time. Your biggest expense will be a pair of SMA >>>>>>connectors per fixture. >>>>>> >>>>>>If you want more information on bypass network design, Istvan's web >>>>>> >>>>site, >>>> >>>> >>>>>>the Teraspeed web site, and the X2Y web site all have papers on the >>>>>> >>>>>subject. >>>>> >>>>> >>>>>>Steve. >>>>>>At 04:58 PM 5/16/2005 +0530, Joe Paul M wrote: >>>>>> >>>>>> >>>>>> >>>>>> >>>>>>>I have a doubt regarding decoupling capacitors. >>>>>>> >>>>>>>I have the option for using 1 uf9AVX 06036D105KAT2A) or 0.1uF (AVX >>>>>>>0603ZC104KAT2A) at same cost. >>>>>>> >>>>>>>Concerned rise time is about 2nS. >>>>>>> >>>>>>>Is there any issue in using 1uF caps, if it has same ESR and ESL and >>>>>>>package (0603) as 0.1uF. >>>>>>> >>>>>>>Thanks all >>>>>>>Joe Paul >>>>>>> >>>>>>>------------------------------------------------------------------ >>>>>>>To unsubscribe from si-list: >>>>>>>si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field >>>>>>> >>>>>>>or to administer your membership from a web page, go to: >>>>>>>//www.freelists.org/webpage/si-list >>>>>>> >>>>>>>For help: >>>>>>>si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field >>>>>>> >>>>>>>List FAQ wiki page is located at: >>>>>>> http://si-list.org/wiki/wiki.pl?Si-List_FAQ >>>>>>> >>>>>>>List technical documents are available at: >>>>>>> http://www.si-list.org >>>>>>> >>>>>>>List archives are viewable at: >>>>>>> //www.freelists.org/archives/si-list >>>>>>>or at our remote archives: >>>>>>> http://groups.yahoo.com/group/si-list/messages >>>>>>>Old (prior to June 6, 2001) list archives are viewable at: >>>>>>> http://www.qsl.net/wb6tpu >>>>>>> >>>>>>> >>>>>> >>>>>>------------------------------------------------------------------ >>>>>>To unsubscribe from si-list: >>>>>>si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field >>>>>> >>>>>>or to administer your membership from a web page, go to: >>>>>>//www.freelists.org/webpage/si-list >>>>>> >>>>>>For help: >>>>>>si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field >>>>>> >>>>>>List FAQ wiki page is located at: >>>>>> http://si-list.org/wiki/wiki.pl?Si-List_FAQ >>>>>> >>>>>>List technical documents are available at: >>>>>> http://www.si-list.org >>>>>> >>>>>>List archives are viewable at: >>>>>> //www.freelists.org/archives/si-list >>>>>>or at our remote archives: >>>>>> http://groups.yahoo.com/group/si-list/messages >>>>>>Old (prior to June 6, 2001) list archives are viewable at: >>>>>> http://www.qsl.net/wb6tpu >>>>>> >>>>>> >>>>>> >>>>>------------------------------------------------------------------ >>>>>To unsubscribe from si-list: >>>>>si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field >>>>> >>>>>or to administer your membership from a web page, go to: >>>>>//www.freelists.org/webpage/si-list >>>>> >>>>>For help: >>>>>si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field >>>>> >>>>>List FAQ wiki page is located at: >>>>> http://si-list.org/wiki/wiki.pl?Si-List_FAQ >>>>> >>>>>List technical documents are available at: >>>>> http://www.si-list.org >>>>> >>>>>List archives are viewable at: >>>>> //www.freelists.org/archives/si-list >>>>>or at our remote archives: >>>>> http://groups.yahoo.com/group/si-list/messages >>>>>Old (prior to June 6, 2001) list archives are viewable at: >>>>> http://www.qsl.net/wb6tpu >>>>> >>>>> >>>>> >>>>>______________________________________________________________________ >>>>>All email being sent to or from SRC Computers, Inc. will be scanned by a >>>>>third party scanning service. >>>>>______________________________________________________________________ >>>>> >>>> >>>>______________________________________________________________________ >>>>All email being sent to or from SRC Computers, Inc. will be scanned by a >>>>third party scanning service. >>>>______________________________________________________________________ >>>> >>> >>>______________________________________________________________________ >>>All email being sent to or from SRC Computers, Inc. will be scanned by a >>>third party scanning service. >>>______________________________________________________________________ >>> >> >> >>------------------------------------------------------------------ >>To unsubscribe from si-list: >>si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field >> >>or to administer your membership from a web page, go to: >>//www.freelists.org/webpage/si-list >> >>For help: >>si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field >> >>List FAQ wiki page is located at: >> http://si-list.org/wiki/wiki.pl?Si-List_FAQ >> >>List technical documents are available at: >> http://www.si-list.org >> >>List archives are viewable at: >> //www.freelists.org/archives/si-list >>or at our remote archives: >> http://groups.yahoo.com/group/si-list/messages >>Old (prior to June 6, 2001) list archives are viewable at: >> http://www.qsl.net/wb6tpu >> >> >> >> > >-- > >Ludwig Systems Engineering Consulting - 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