[SI-LIST] Re: Decoupling capacitors
- From: steve weir <weirsi@xxxxxxxxxx>
- To: Larry.Smith@xxxxxxx
- Date: Mon, 16 May 2005 14:32:06 -0700
Larry, yes and no. From my studies, yes the big "V" does have a lower ESR,
typically 35 to 40% that of an optimized multipole approach. And yes this
does result in higher impedance peaking when the discrete capacitor network
forms a parallel resonant tank with the board structure at a frequency that
is below the half wavelength of the board structure. But in general, I
don't care much and don't need to.
From a power delivery standpoint all sane ICs have package power cut-off
that is far below this resonance and power is not affected. If the boards
are stacked up and routed properly the discrete cap to board AR has no
effect on signaling. There is a rare case for EMC where one may have a
clock or major signal harmonic that lines right up on the AR. In this case
adjusting the cavity or capacitors can shift the peak. However, we see a
similar problem with the natural half wave resonances of the major board
propagation modes and those occur at higher frequencies usually closer to
coherent sources like clocks. There is little we can do with capacitors
about that problem. Altering the cavities is the answer there. And when
we do shrink the cavity sizes, guess what? The AR of the discrete caps
moves up in frequency as well.
On the low frequency side, design of the power system needs to include the
VRM and output capacitor network. This can be annoying when using off the
shelf converters that emphasize size but can as you note fail to provide
proper damping. If one uses the multipole approach we do have a higher
ESR, and achieving a peak free response with an OTS converter is
easier. If one is the converter designer, then your approach can
theoretically be used to design a flat network from audio on up. However,
with sufficient capacitance, the ripple with the big "V" can usually be mad
more than adequate. If not, then additional pole(s) can be added. (
Usually one is enough. ) At the low frequency end, flexibility with
capacitor values fades, and a properly selected tantalum can do a world of
good. In this regard the NEC Proadlizers look interesting as well.
There are different ways to skin this cat, and while I prefer the big "V" I
have the utmost admiration for the effort and elegance in the fine
multipole method that you prefer.
Best Regards,
Steve.
At 09:14 AM 5/16/2005 -0700, Larry SMITH wrote:
>Steve - The "big V" approach makes a very low impedance at the series
>resonant frequency of the capacitor chosen. With this method, problems
>can arise about a decade above and below the SRF where the decoupling
>capacitors have to interface with other components in the system.
>
>On the low frequency side, the output of the VRM is inductive. It's
>impedance crosses the capacitive impedance of all the big V caps in
>parallel and usually makes a fairly high Q resonant peak in the kHz or
>low MHz region.
>
>On the other end of the spectrum, the inductance of all the caps in
>parallel usually resonates with the capacitance of the power planes and
>make a high Q resonant peak in the 100MHz region. These are the two
>"gotcha's" associated with the big V method. "Antiresonant" peaks at
>any frequecy can (and often does) cause trouble in power distribution
>systems.
>
>You can add additional capacitor values to address the newly created
>peaks, but then you end up with more peaks.. If you add enough
>capacitor values to eliminate all the peaks, you end up with a flat
>frequency profile. This is the one I like.
>
>regards,
>Larry Smith
>Sun Microsystems
>
>steve weir wrote:
> > Joe Paul, the ESL may be the same but the ESR of the 1uF in the same
> > chemistry and voltage will definitely be about 35-40% that of the
> > 0.1uF. It is very unlikely that 0.1uF will provide any cost or
> performance
> > advantage over 1uF in the same 0603 case from the same mfg at a low
> voltage
> > rating. Due to cover layer considerations, depending on the voltage and
> > chemistry, the 1uF may actually exhibit lower mounted inductance than
> the 0.1uF
> >
> > At 2ns/ 160MHz, both capacitors are fully inductive and cover layer issues
> > aside will have very similar performance. The 1.0uF capacitor has the
> > benefit of more capacitance which generally makes it easier to stabilize
> > the transition from the bulk capacitors / VRM. Fans of the big "V" like
> > Dr. Johnson, Istvan Novak, and myself will usually advise that at the
> same:
> > cost, package size and chemistry, take the bigger capacitor. If you want
> > to find out why some people do things differently, take a look at Larry
> > Smith and company's papers on multipole capacitor networks. If nothing
> > else, those papers should help you better understand what you are doing
> > whether or not you elect to follow the methods they describe.
> >
> > If you really want to see how your capacitors perform and have access to a
> > VNA, I suggest building a test board. You can get details on such a board
> > from Istvan's papers on his web site, or from mine on the X2Y web
> > site. You can put together a decent set of CPW test fixtures for under
> > $200. cash and some time. Your biggest expense will be a pair of SMA
> > connectors per fixture.
> >
> > If you want more information on bypass network design, Istvan's web site,
> > the Teraspeed web site, and the X2Y web site all have papers on the
> subject.
> >
> >
> > Steve.
> > At 04:58 PM 5/16/2005 +0530, Joe Paul M wrote:
> >
> >
> >>I have a doubt regarding decoupling capacitors.
> >>
> >>I have the option for using 1 uf9AVX 06036D105KAT2A) or 0.1uF (AVX
> >>0603ZC104KAT2A) at same cost.
> >>
> >>Concerned rise time is about 2nS.
> >>
> >>Is there any issue in using 1uF caps, if it has same ESR and ESL and
> >>package (0603) as 0.1uF.
> >>
> >>Thanks all
> >>Joe Paul
> >>
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