[SI-LIST] Re: Decoupling capacitors
- From: steve weir <weirsi@xxxxxxxxxx>
- To: "Ken Cantrell" <Ken.Cantrell@xxxxxxxxxxxxxxxx>, <Larry.Smith@xxxxxxx>
- Date: Mon, 16 May 2005 14:44:59 -0700
Ken, please see also my comments to Larry. Please do review, because it is
not as nearly black and white as you think. The price for reduced
capacitor count is a higher inductance in the capacitor network. Do we
care? Well that all depends on how sharp and uniform a cut-off one
presumes for the IC packages. ( Assuming of course we are using bypass
capacitors to bypass power and not signals. ) If that cut-off is not sharp
or uniform, then at the end of the day equal inductance is what we seek and
the quantity advantage of the fine multipole evaporates. If one makes what
I consider a mistake, but is still done, of relying on the power bypass
network for signal return, then the bypass network is further enlisted to
support much higher frequencies. This is I feel very good at one
thing: making assemblies more expensive.
In my highly opinionated view, the Intel 8 layer server stack-up should be
the basis of a required one or two week course for all SI and PI
engineers. Big "V" works great on those boards designed and built to very,
very demanding cost targets, while supporting behemoth processors and big
fast front-side busses. It is a shining example of using the principles
that experts like Chris have been driving home here for a long time.
Big "V" is not without its limitations. Neither is fine multipole. In the
hands of an experienced engineer, each can be used effectively. Fine
multipole or what I prefer to call F^N was developed by smart people at Sun
to solve a problem and they succeeded. It just doesn't make it the only
viable solution.
Regards,
Steve.
At 11:21 AM 5/16/2005 -0600, Ken Cantrell wrote:
>Gosh -
>"In many common cases, it is just a rote practice that provides no
>actual value. Life with SMT devices is much different today than when we
>had leaded devices and those practices were first adopted."
>I know this has been a long, ongoing issue, and I've read the majority of
>Steve's and Istvan's material. Maybe I need to review. However, if you
>take any Zo vs Frequency (100KHz to 100MHz)profile with a target impedance,
>and plot big V vs Larry's method, you always end up with fewer caps with
>Larry's method, and it's more like a 20% to 30% reduction in count over big
>V. And you don't have any abrupt impedance changes at the ends, just a bunch
>of little cycloids that are near or at the target impedance line. At least
>that's what my handy-dandy copy of D. Brooks' Bypass Impedance Calculator
>shows.
>The real issue, at least for me, is what Larry states below about low and
>high fequency anti-resonances. How do you, Steve/Howard/Istvan, address
>this?
>
>Not a big fan of big V,
>
>Ken
>
>
>-----Original Message-----
>From: si-list-bounce@xxxxxxxxxxxxx
>[mailto:si-list-bounce@xxxxxxxxxxxxx]On Behalf Of Larry SMITH
>Sent: Monday, May 16, 2005 10:14 AM
>To: weirsi@xxxxxxxxxx
>Cc: joepaul@xxxxxxxxxxx; si-list@xxxxxxxxxxxxx
>Subject: [SI-LIST] Re: Decoupling capacitors
>
>
>Steve - The "big V" approach makes a very low impedance at the series
>resonant frequency of the capacitor chosen. With this method, problems
>can arise about a decade above and below the SRF where the decoupling
>capacitors have to interface with other components in the system.
>
>On the low frequency side, the output of the VRM is inductive. It's
>impedance crosses the capacitive impedance of all the big V caps in
>parallel and usually makes a fairly high Q resonant peak in the kHz or
>low MHz region.
>
>On the other end of the spectrum, the inductance of all the caps in
>parallel usually resonates with the capacitance of the power planes and
>make a high Q resonant peak in the 100MHz region. These are the two
>"gotcha's" associated with the big V method. "Antiresonant" peaks at
>any frequecy can (and often does) cause trouble in power distribution
>systems.
>
>You can add additional capacitor values to address the newly created
>peaks, but then you end up with more peaks.. If you add enough
>capacitor values to eliminate all the peaks, you end up with a flat
>frequency profile. This is the one I like.
>
>regards,
>Larry Smith
>Sun Microsystems
>
>steve weir wrote:
> > Joe Paul, the ESL may be the same but the ESR of the 1uF in the same
> > chemistry and voltage will definitely be about 35-40% that of the
> > 0.1uF. It is very unlikely that 0.1uF will provide any cost or
>performance
> > advantage over 1uF in the same 0603 case from the same mfg at a low
>voltage
> > rating. Due to cover layer considerations, depending on the voltage and
> > chemistry, the 1uF may actually exhibit lower mounted inductance than the
>0.1uF
> >
> > At 2ns/ 160MHz, both capacitors are fully inductive and cover layer issues
> > aside will have very similar performance. The 1.0uF capacitor has the
> > benefit of more capacitance which generally makes it easier to stabilize
> > the transition from the bulk capacitors / VRM. Fans of the big "V" like
> > Dr. Johnson, Istvan Novak, and myself will usually advise that at the
>same:
> > cost, package size and chemistry, take the bigger capacitor. If you want
> > to find out why some people do things differently, take a look at Larry
> > Smith and company's papers on multipole capacitor networks. If nothing
> > else, those papers should help you better understand what you are doing
> > whether or not you elect to follow the methods they describe.
> >
> > If you really want to see how your capacitors perform and have access to a
> > VNA, I suggest building a test board. You can get details on such a board
> > from Istvan's papers on his web site, or from mine on the X2Y web
> > site. You can put together a decent set of CPW test fixtures for under
> > $200. cash and some time. Your biggest expense will be a pair of SMA
> > connectors per fixture.
> >
> > If you want more information on bypass network design, Istvan's web site,
> > the Teraspeed web site, and the X2Y web site all have papers on the
>subject.
> >
> >
> > Steve.
> > At 04:58 PM 5/16/2005 +0530, Joe Paul M wrote:
> >
> >
> >>I have a doubt regarding decoupling capacitors.
> >>
> >>I have the option for using 1 uf9AVX 06036D105KAT2A) or 0.1uF (AVX
> >>0603ZC104KAT2A) at same cost.
> >>
> >>Concerned rise time is about 2nS.
> >>
> >>Is there any issue in using 1uF caps, if it has same ESR and ESL and
> >>package (0603) as 0.1uF.
> >>
> >>Thanks all
> >>Joe Paul
> >>
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