Hi Chris, Sorry for the late reply; I was busy after work tonight. Thank you
for reading my paper "On-chip Jitter and system Power Integrity" DesignCon 2012.
You are still having in mind a design and how we can improve it, but this is
not a case. This paper main goals were:Â 1) to describe the method for PDN
validation through Jitter measurements which less impacted by parasitic and
applicable for any ICs weather they have special features, or not, that other
methods require;Â 2) using this method we revealed Jitter resonance induced by
PDN noise that origin of switching on-die logic.   Note, that this is a
characteristic of PDN performance "looking from the die side".3) next, using
this method we researched how on-board decoupling impacts the PDN resonances.Â
Â
The method: two logic domains in standard FPGA were used that share the same
PDN; one logic domain was used as an Aggressor, and other as a Victim. Both
were switching periodically and asynchronously. Switching frequency
sequentially changing and Jitter of a Victim was each time measured. Jitter
resonance: switching of an aggressor creates pulses of a current
corresponding each rise and fall time of Aggressor signal; these current pulses
causes PDN voltage variations (noise). Changing Aggressor frequency we change
noise frequency; when noise frequency reaches PDN resonance the impact on the
Victim became higher and victim Jitter reaches the peak. So, this is a way to
find a PDN resonances.   Decoupling: we changed on-board decoupling and
measured Jitter; we obtained that with rising decoupling at 36 MHz the
resonance became stronger and in field 100-200 MHz Jitter slightly reduced -
this effect also explained in paragraph following the graph. These measurements
are time consuming and we did not measure higher resonances. I think that
Jitter reduction at 100-200 MHz with increasing decoupling is an evidence that
higher frequency resonances also became more narrow and higher.  Â
So, we did not sacrifice nothing; we just did an experiment, got data, and
explained the effects.Â
I was glad to see Binayak' good explanation of the effect that I also got from
these experiments: looking from die capacitance through package inductance to
the decoupling we see parallel resonance. Its' ESR is decreasing with rising
number of the capacitances. When ESR is decreased, Q-factor rising and, also,
the resonance peak.  Â
Chris, I agree with you that these results are important as an illustration of
new effects that has not been noted before: particular, it was demonstrated
that the traditional approachto the reducing PDN resonances by increasing the
decoupling on PCB does not help toremove resonance peaks. Otherwise,lowering
the PCB impedance by adding more capacitances makes the situation evenworse, -
the values of the peaks increase.
I will be glad to continue this discussion, which is very interesting for me
personally. However might be not all Si-listers are interested in it;Â should
we move it off-line?
Best regards, Iliya Â
On Wednesday, August 29, 2018, 4:59:50 PM PDT, Cheng, Chris
<chris.cheng@xxxxxxx> wrote:
Your clarification makes me even more puzzled about your conclusions. If this
is general one die core noise to clock tree buffer power, why would you
sacrifice the critical >100MHz noise damping that most core logic will care for
the 30MHz or so that most switching logic don't care ? Is your chip only
working in 30-40MHz ?
Back to the PLL jitter issue. As long as the clock buffer output is used for
the PLL phase detector input, it is still part of the closed PLL controlled
loop. You can see below 20MHz the PLL loop bandwidth corrected the induced
jitter on the clock tree buffer. You just luck out that when the reduced cap
configuration peaked around 10MHz, that was below the PLL loop bandwidth. Had
the PLL loop bandwidth is forced to be lowered by crazy PLL spec like PCIE to
5MHz, the 10MHz peaking of the red curve will most probably be higher than the
high cap count configuration peak around 35MHz.Â
Sorry, these are important design trade-offs that I am not sure you have drawn
the right conclusion. We should keep this discussion going.
Chris Cheng
Distinguished Technologist , Electrical
Hewlett-Packard Enterprise Company
Â
+1 510 344 4439/ TelÂ
chris.cheng@xxxxxxx / EmailÂ
940 N. McCarthy Blvd., Milpitas, CA 95035
USA
From: Iliya Zamek [mailto:i_zamek@xxxxxxxxx]Â
Sent: Wednesday, August 29, 2018 1:28 PM
To: Cheng, Chris <chris.cheng@xxxxxxx>
Cc: dmarc-noreply@xxxxxxxxxxxxx; binayaks@xxxxxxxxx <binayaks@xxxxxxxxx>;Â
tom@xxxxxxxxxxxxxxxxx; si-list@xxxxxxxxxxxxx <si-list@xxxxxxxxxxxxx>; FRED
MOTTER <motter@xxxxxxxxxxxxx>; FRED B <FRED@xxxxxxxxxxxxx>; Jacques Tazartes
<jacquest15@xxxxxxxxxxxxx>; EmadIbrahim <EIbrahim@xxxxxxxxx>;Â
Myrna5@xxxxxxxxxxxxxx <Myrna5@xxxxxxxxxxxxxx>; Istvan Novak
<istvan.novak@xxxxxxxxxxx>;Â junichi.yamada.ak@xxxxxxxxxxxÂ
<junichi.yamada.ak@xxxxxxxxxxx>; Cosmin Iorga <ci42775@xxxxxxxxx>
Subject: Re: [SI-LIST] Re: Controlled ESR capacitor
Hi Chris,
Thank you for your comments.Â
Both, 30-40 and 100-200 MHz jitterÂ
components are important. There is noÂ
point to sacrifice one, or other.Â
This was special experiment to validate Â
the role of board decoupling onÂ
interaction of two logic domains insideÂ
the chip which shared the sameÂ
power supply: core logic was switchingÂ
(Aggressor) impacting routingÂ
component's and clock tree' jitter (victims).Â
 PLL on clock tree was using other, quietÂ
power supply. Scale is the same as onÂ
figure 4: (jitter at core switching)/(jitterÂ
at core quiet).
Let me know if you have more questions.
Thank you.
Iliya
On Aug 29, 2018 11:10 AM, "Cheng, Chris" <chris.cheng@xxxxxxx> wrote:
Why do you think it is worth sacrificing the 100-200MHz jitter performance with
high cap count for the narrow range of 30-40MHz jitter performance with lower
cap count ?Â
In the world of XbitY coding for the 10+Gb/s world, I would think the
100-200Mhz jitter performance is much more important than those 30-40MHz.Â
To me, the best conclusion I can draw from the two graph seems to point out the
price we pay for the obsession of jitter transfer over jitter accumulation.
Clearly the 30-40Mhz jitter peaking could be fixed by uping the PLL loop
bandwidth from around 10MHz to 40+MHz. In the name of saving a few $ in cheap
clock source, we paid this price for all PLL jitter accumulation downstream.Â
To recap :Â
a) Who would feed a PLL with raw unfiltered power and rely on decoupling cap
ESR to maintain PLL jitter performance ?Â
b) Why is it worth sacrificing 100-200MHz jitter performance to a lower band
30-40MHz ?Â
Also, what was the vertical scale of the graphs ?Â
Chris ChengÂ
Distinguished Technologist , ElectricalÂ
Hewlett-Packard Enterprise CompanyÂ
 Â
+1 510 344 4439/ TelÂ
chris.cheng@xxxxxxx / EmailÂ
940 N. McCarthy Blvd., Milpitas, CA 95035Â
USAÂ
-----Original Message-----Â
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On ;
Behalf Of Iliya ZamekÂ
Sent: Monday, August 27, 2018 8:39 PMÂ
To:Â binayaks@xxxxxxxxxÂ
Cc:Â dmarc-noreply@xxxxxxxxxxxxx; Cheng, Chris <chris.cheng@xxxxxxx>;Â
tom@xxxxxxxxxxxxxxxxx;Â si-list@xxxxxxxxxxxxx; FRED MOTTER
<motter@xxxxxxxxxxxxx>; FRED B <FRED@xxxxxxxxxxxxx>; Jacques Tazartes
<jacquest15@xxxxxxxxxxxxx>; EmadIbrahim <EIbrahim@xxxxxxxxx>;Â
Myrna5@xxxxxxxxxxxxxx; Istvan Novak <istvan.novak@xxxxxxxxxxx>;Â
junichi.yamada.ak@xxxxxxxxxxx; Cosmin Iorga <ci42775@xxxxxxxxx>Â
Subject: [SI-LIST] Re: Controlled ESR capacitorÂ
Somehow my email was distorted. Re-sending. Â
Hi Binayak,Â
Your effect description is correct.Â
If you look at papers which links were included in my email sent 2 days ago
(August 25) you can see the graphà that described exactly the same - how low
PCB impedance causes rising on-die transients.Â
If you could not find these papers, you might connect me off-line and I'll send
it to you.Â
Thank you.Â
Iliya.Â
intensive on-board decoupling does not reduce PDN resonances respect to the
chip die, but even make PDN performance worse, - resonances are rising.Â
I will be glad to continue this discussion, however might be not all Si-listers
are interested in it and we should move it off-line?
Best regards, Iliya Â
On Wednesday, August 29, 2018, 4:59:50 PM PDT, Cheng, Chris
<chris.cheng@xxxxxxx> wrote:
Your clarification makes me even more puzzled about your conclusions. If this
is general one die core noise to clock tree buffer power, why would you
sacrifice the critical >100MHz noise damping that most core logic will care for
the 30MHz or so that most switching logic don't care ? Is your chip only
working in 30-40MHz ?
Back to the PLL jitter issue. As long as the clock buffer output is used for
the PLL phase detector input, it is still part of the closed PLL controlled
loop. You can see below 20MHz the PLL loop bandwidth corrected the induced
jitter on the clock tree buffer. You just luck out that when the reduced cap
configuration peaked around 10MHz, that was below the PLL loop bandwidth. Had
the PLL loop bandwidth is forced to be lowered by crazy PLL spec like PCIE to
5MHz, the 10MHz peaking of the red curve will most probably be higher than the
high cap count configuration peak around 35MHz.
Sorry, these are important design trade-offs that I am not sure you have drawn
the right conclusion. We should keep this discussion going.
Chris Cheng
Distinguished Technologist , Electrical
Hewlett-Packard Enterprise Company
Â
+1 510 344 4439/ Tel
chris.cheng@xxxxxxx / Email
940 N. McCarthy Blvd., Milpitas, CA 95035
USA
From: Iliya Zamek [mailto:i_zamek@xxxxxxxxx] ;
Sent: Wednesday, August 29, 2018 1:28 PM
To: Cheng, Chris <chris.cheng@xxxxxxx>
Cc: dmarc-noreply@xxxxxxxxxxxxx; binayaks@xxxxxxxxx <binayaks@xxxxxxxxx>;
tom@xxxxxxxxxxxxxxxxx; si-list@xxxxxxxxxxxxx <si-list@xxxxxxxxxxxxx>; FRED
MOTTER <motter@xxxxxxxxxxxxx>; FRED B <FRED@xxxxxxxxxxxxx>; Jacques Tazartes
<jacquest15@xxxxxxxxxxxxx>; EmadIbrahim <EIbrahim@xxxxxxxxx>;
Myrna5@xxxxxxxxxxxxxx <Myrna5@xxxxxxxxxxxxxx>; Istvan Novak
<istvan.novak@xxxxxxxxxxx>; junichi.yamada.ak@xxxxxxxxxxx
<junichi.yamada.ak@xxxxxxxxxxx>; Cosmin Iorga <ci42775@xxxxxxxxx>
Subject: Re: [SI-LIST] Re: Controlled ESR capacitor
Hi Chris,
Thank you for your comments.Â
Both, 30-40 and 100-200 MHz jitterÂ
components are important. There is noÂ
point to sacrifice one, or other.Â
This was special experiment to validate Â
the role of board decoupling onÂ
interaction of two logic domains insideÂ
the chip which shared the sameÂ
power supply: core logic was switchingÂ
(Aggressor) impacting routingÂ
component's and clock tree' jitter (victims).Â
 PLL on clock tree was using other, quietÂ
power supply. Scale is the same as onÂ
figure 4: (jitter at core switching)/(jitterÂ
at core quiet).
Let me know if you have more questions.
Thank you.
Iliya
On Aug 29, 2018 11:10 AM, "Cheng, Chris" <chris.cheng@xxxxxxx> wrote:
Why do you think it is worth sacrificing the 100-200MHz jitter performance with
high cap count for the narrow range of 30-40MHz jitter performance with lower
cap count ?
In the world of XbitY coding for the 10+Gb/s world, I would think the
100-200Mhz jitter performance is much more important than those 30-40MHz.
To me, the best conclusion I can draw from the two graph seems to point out the
price we pay for the obsession of jitter transfer over jitter accumulation.
Clearly the 30-40Mhz jitter peaking could be fixed by uping the PLL loop
bandwidth from around 10MHz to 40+MHz. In the name of saving a few $ in cheap
clock source, we paid this price for all PLL jitter accumulation downstream.
To recap :
a) Who would feed a PLL with raw unfiltered power and rely on decoupling cap
ESR to maintain PLL jitter performance ?
b) Why is it worth sacrificing 100-200MHz jitter performance to a lower band
30-40MHz ?
Also, what was the vertical scale of the graphs ?
Chris Cheng
Distinguished Technologist , Electrical
Hewlett-Packard Enterprise Company
Â
+1 510 344 4439/ Tel
chris.cheng@xxxxxxx / Email
940 N. McCarthy Blvd., Milpitas, CA 95035
USA
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On ;
Behalf Of Iliya Zamek
Sent: Monday, August 27, 2018 8:39 PM
To: binayaks@xxxxxxxxx
Cc: dmarc-noreply@xxxxxxxxxxxxx; Cheng, Chris <chris.cheng@xxxxxxx>;
tom@xxxxxxxxxxxxxxxxx; si-list@xxxxxxxxxxxxx; FRED MOTTER
<motter@xxxxxxxxxxxxx>; FRED B <FRED@xxxxxxxxxxxxx>; Jacques Tazartes
<jacquest15@xxxxxxxxxxxxx>; EmadIbrahim <EIbrahim@xxxxxxxxx>;
Myrna5@xxxxxxxxxxxxxx; Istvan Novak <istvan.novak@xxxxxxxxxxx>;
junichi.yamada.ak@xxxxxxxxxxx; Cosmin Iorga <ci42775@xxxxxxxxx>
Subject: [SI-LIST] Re: Controlled ESR capacitor
Somehow my email was distorted. Re-sending.Â
Hi Binayak,
Your effect description is correct.
If you look at papers which links were included in my email sent 2 days ago
(August 25) you can see the graphà that described exactly the same - how low
PCB impedance causes rising on-die transients.
If you could not find these papers, you might connect me off-line and I'll send
it to you.
Thank you.
Iliya.
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