We can use controlled-ESR capacitors to reduce or eliminate all sorts of
resonances: DC-DC converter peaking, inter-capacitor resonances,
plane-capacitor resonances and plane modal resonances, as well as
limiting the Q of LC filters. There are also other uses and benefits,
which one day may find their way into a DesignCon paper. I have
advocated controlled-ESR capacitors for twenty years and helped to
create some. This having said I never say they must be used: in some
applications they may make sense and we can use them if the
cost/performance analysis leads us that way. And there are other
(numerous) cases when they are not needed. The important thing is to
understand the pros and cons, benefits and downsides, for all of our
possible PDN implementations, including possible implementations with
controlled-ESR capacitors and to make an educated decision.
Regards,
Istvan Novak
On 8/27/2018 4:06 PM, Grasso, Charles wrote:
Istvan can speak to this better than I can , however it is my understanding
that the intention is to terminate the pwr/gnd plane transmission line.
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On ;
Behalf Of Cheng, Chris
Sent: Monday, August 27, 2018 2:45 AM
To: binayaks@xxxxxxxxx; dmarc-noreply@xxxxxxxxxxxxx
Cc: tom@xxxxxxxxxxxxxxxxx; si-list@xxxxxxxxxxxxx; FRED MOTTER
<motter@xxxxxxxxxxxxx>; FRED B <FRED@xxxxxxxxxxxxx>; Jacques Tazartes
<jacquest15@xxxxxxxxxxxxx>; EmadIbrahim <EIbrahim@xxxxxxxxx>;
Myrna5@xxxxxxxxxxxxxx; Istvan Novak <istvan.novak@xxxxxxxxxxx>;
junichi.yamada.ak@xxxxxxxxxxx
Subject: [SI-LIST] Re: Controlled ESR capacitor
Sorry I have to ask the same question again. What exactly are these
controlled ESR caps for ?
I heard of use for voltage regulator control loop/filtering , nothing to do
with SI.
I heard of ESR control for the ferrite/Inductor for the PLL filtering to
control the Q.
But for general purpose power decoupling needing ESR control ? Seriously ?
Chris Cheng
Distinguished Technologist , Electrical
Hewlett-Packard Enterprise Company
+1 510 344 4439/ Tel
chris.cheng@xxxxxxx / Email
940 N. McCarthy Blvd., Milpitas, CA 95035 USA
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On ;
Behalf Of Binayak Shrestha
Sent: Sunday, August 26, 2018 12:59 AM
To: dmarc-noreply@xxxxxxxxxxxxx
Cc: tom@xxxxxxxxxxxxxxxxx; si-list@xxxxxxxxxxxxx; FRED MOTTER
<motter@xxxxxxxxxxxxx>; FRED B <FRED@xxxxxxxxxxxxx>; Jacques Tazartes
<jacquest15@xxxxxxxxxxxxx>; EmadIbrahim <EIbrahim@xxxxxxxxx>;
Myrna5@xxxxxxxxxxxxxx; Istvan Novak <istvan.novak@xxxxxxxxxxx>;
junichi.yamada.ak@xxxxxxxxxxx
Subject: [SI-LIST] Re: Controlled ESR capacitor
Good luck in convincing your vendor to provide information like on-die
capacitance, package inductance, etc.
Worst case is that they may not even have characterized them! I have faced
such cases SO MANY times!
binayak
On Sunday, August 26, 2018, Iliya Zamek <dmarc-noreply@xxxxxxxxxxxxx> wrote:
Thanks to Yamada,--
For starting this very good discussion.
As Cosmin Iorga and Istvan Novak pointed, if the old method worked in
70's and 80's it might not work at modern technology. In Altera and
after we saw that this happened starting 120- and 90-nm devices,
already. To address new effects associated with increased transient
noise many companies started to study of on-Chip Dynamic current,
on-die structure, and how its impact the PDN and product performance.
Particular, as Cosmin noted, different configuration of FPGA, or
different mode of a microprocessor might produce different Dynamic
current profile and might require different approach for the PDN
design, including decoupling. High ESR capacitances appeared as one of
the attempt to fight modern system resonances. Number of companies
started experimenting with high ESR capacitances: Oracle - as pointed
and referenced by Istvan, in Altera we did it with capacitances from
TDK and Sanyo Electric Co. Ltd.
We know some groups in different companies which are also using high
ESR capacitances without publishing it. I also could not demonstrate,
for now, how ESR caps may improve PDN, but instead, I have published
an example how increasing number of decoupling capacitors leads to
rising PDN resonances: we decreased number of decoupling capacitances
and measured Jitter resonance induced by PDN noise, - the resonance
peak was reduced at decreasing number of capacitances, and, hence,
increasing system ESR.
You might see these results in paper “On-chipJitter and system Power
Integrity” DesignCon 2012,
and Tutorial “Does'better' PDN result in better product performance?”
DesignCon 2015.
Thank you.
Iliya Zamek
On Friday, August 24, 2018, 11:02:33 PM PDT, Cosmin Iorga <
dmarc-noreply@xxxxxxxxxxxxx> wrote:
Interesting discussion - here are some more thoughts: From a
simplified perspective "sprinkling" capacitors throughout the power
planes combined with the mounting inductance and planes cavity
parasitics creates multiple RLC type resonant loops "sprinkled" throughout
the power plane region.
Intuitively, it is now a matter of frequency spectrum of the power
supply transient currents to decide if the multitude of RLC resonant
structures help or not. If this method worked in 70's and 80's (for
those typical operating frequencies and rise/fall times) it does not
necessarily mean that it will work these days. It all depends on how
the spectral components of the power supply transient currents overlap
with the resonance frequencies of these "sprinkled" RLC resonant
structures. An FPGA for example may generate different transient
supply currents for different configurations, and on the same board if
we load one configuration file we may see improvement from this
capacitor "sprinklin g" te chnique and if we load a different
configuration file we may see no improvement or even degradation of
the PDN performance. So in my opinion there is no unique answer to
whether the capacitor sprinkling technique works or not.
Regards,
Cosmin
http://www.piscanner.com
--------------------------------------------
On Fri, 8/24/18, Bob B <Myrna5@xxxxxxxxxxxxxx> wrote:
Subject: [SI-LIST] Re: Controlled ESR capacitor
To: tom@xxxxxxxxxxxxxxxxx, si-list@xxxxxxxxxxxxx, "'FRED MOTTER'" <
motter@xxxxxxxxxxxxx>, "FRED B" <FRED@xxxxxxxxxxxxx>, "Jacques
Tazartes" < jacquest15@xxxxxxxxxxxxx>, "Ibrahim, Emad"
<EIbrahim@xxxxxxxxx>
Date: Friday, August 24, 2018, 3:46 PM
Tom, I agree.
Worked at Litton Industries, Teledyne Systems and Northrop Grumman
as Signal Integrity Manager from 70's till 2006. Working with Two
EMC counterparts, we improved test results, yield and success when
we added and critically placed decoupling caps to circuit board
layouts.
Capacitor design and selection was one of my responsibilities early
on.
Also oscillator design and research. I added these experiences
because it helped reinforce the analysis. Hope our hands-on
experience helps.
Bob Bremer, retired.
On 8/24/2018 3:41 PM, Tom Dagostino
wrote:
> Lee
>
> I don't agree with your last
statement. If people have found important > information but can't
share the details it is still good knowledge to know > their
conclusions. It allows others to go down the path and verify for >
themselves if the stated results are correct. It at least points to
a path > that might be worth exploring.
>
> Regards
>
> Tom Dagostino
> 971-279-5325
> tom@xxxxxxxxxxxxxxxxx
>
> Teraspeed Labs
> 9999 SW Wilshire Street
> Suite 102
> Portland, OR 97225
>
> -----Original Message-----
> From: si-list-bounce@xxxxxxxxxxxxx
[mailto:si-list-bounce@xxxxxxxxxxxxx]
On
> Behalf Of leeritchey@xxxxxxxxxxxxx
> Sent: Friday, August 24, 2018
12:51 PM
> To: 'Ravinder Ajmani'; CHARLES.GRASSO@xxxxxxxx;
joel.brown@xxxxxxxxxx; > ken.patterson@xxxxxxxxxxxxxxxxx > Cc:
asparky@xxxxxxxxxxxxxxxxxxxxxxxx; 'Istvan Novak'; >
junichi.yamada.ak@xxxxxxxxxxx; 'SI-List'
> Subject: [SI-LIST] Re: Controled
ESR capacitor
>
> Ravinder,
>
> The fact that a simulator shows
some change as capacitors are moved isn't > enough to conclude that
this will make a difference in EMI or anything else.
> If there is good test data
that supports this as significant, it needs to > be shown or this
should not be offered as a design rule. Even then, there > needs to
be limits offered as to when the rules apply.
>
> I often hear the statement that
the results are company confidential as the > reason the proof
cannot be published. If that is the case, the rules should > not be
offered on this forum.
>
>
> -----Original Message-----
> From: Ravinder Ajmani <ravinder.ajmani@xxxxxxx> > Sent: Friday,
August 24, 2018
12:42 PM
> To: leeritchey@xxxxxxxxxxxxx;
CHARLES.GRASSO@xxxxxxxx;
> joel.brown@xxxxxxxxxx;
ken.patterson@xxxxxxxxxxxxxxxxx
> Cc: asparky@xxxxxxxxxxxxxxxxxxxxxxxx; 'Istvan Novak'
> <istvan.novak@xxxxxxxxxxx>;
junichi.yamada.ak@xxxxxxxxxxx;
'SI-List'
> <si-list@xxxxxxxxxxxxx>
> Subject: RE: [SI-LIST] Re:
Controled ESR capacitor
>
> Lee,
>
> As you often say, I can't provide
actual data, which is Company
> Confidential. I am attaching
a part of ANSYS workshop showing details of > Resonant Mode
Analysis, which is what I was referring to.
>
> Sorry, other than those on the TO
and CC list will not be able to see the > attachment.
>
> Regards,
>
> Ravinder Ajmani
> Western Digital(r)
> 5601 Great Oaks Pkwy
> San Jose, CA 95119
> Ravinder.Ajmani@xxxxxxx
> www.wdc.com
> Always Do Right. This Will Gratify
Some People and Astonish the Rest ....
> Mark Twain
>
>
>
> -----Original Message-----
> From: leeritchey@xxxxxxxxxxxxx
[mailto:leeritchey@xxxxxxxxxxxxx]
> Sent: Friday, August 24, 2018
11:08 AM
> To: Ravinder Ajmani <ravinder.ajmani@xxxxxxx>;
CHARLES.GRASSO@xxxxxxxx; > joel.brown@xxxxxxxxxx;
ken.patterson@xxxxxxxxxxxxxxxxx > Cc:
asparky@xxxxxxxxxxxxxxxxxxxxxxxx; 'Istvan Novak'
> <istvan.novak@xxxxxxxxxxx>;
junichi.yamada.ak@xxxxxxxxxxx;
'SI-List'
> <si-list@xxxxxxxxxxxxx>
> Subject: RE: [SI-LIST] Re:
Controled ESR capacitor
>
> You have to show me, if you want
me to believe this, because my experience > does not support that
claim.
>
> -----Original Message-----
> From: Ravinder Ajmani <ravinder.ajmani@xxxxxxx> > Sent: Friday,
August 24, 2018
10:59 AM
> To: leeritchey@xxxxxxxxxxxxx;
CHARLES.GRASSO@xxxxxxxx;
> joel.brown@xxxxxxxxxx;
ken.patterson@xxxxxxxxxxxxxxxxx
> Cc: asparky@xxxxxxxxxxxxxxxxxxxxxxxx; 'Istvan Novak'
> <istvan.novak@xxxxxxxxxxx>;
junichi.yamada.ak@xxxxxxxxxxx;
'SI-List'
> <si-list@xxxxxxxxxxxxx>
> Subject: RE: [SI-LIST] Re:
Controled ESR capacitor
>
> Lee,
>
> If you perform a resonance
analysis on any plane pair, you will notice > localized resonances
at different frequencies. If these are close to I/Os > then it can
result in EMI issues.
>
> Regards,
>
> Ravinder Ajmani
> Western Digital(r)
> 5601 Great Oaks Pkwy
> San Jose, CA 95119
> Ravinder.Ajmani@xxxxxxx
> www.wdc.com
> Always Do Right. This Will Gratify
Some People and Astonish the Rest ....
> Mark Twain
>
>
> -----Original Message-----
> From: si-list-bounce@xxxxxxxxxxxxx
[mailto:si-list-bounce@xxxxxxxxxxxxx]
On
> Behalf Of leeritchey@xxxxxxxxxxxxx
> Sent: Friday, August 24, 2018
10:30 AM
> To: CHARLES.GRASSO@xxxxxxxx;
joel.brown@xxxxxxxxxx;
> ken.patterson@xxxxxxxxxxxxxxxxx
> Cc: asparky@xxxxxxxxxxxxxxxxxxxxxxxx; 'Istvan Novak'
> <istvan.novak@xxxxxxxxxxx>;
junichi.yamada.ak@xxxxxxxxxxx;
'SI-List'
> <si-list@xxxxxxxxxxxxx>
> Subject: [SI-LIST] Re: Controled
ESR capacitor
>
> When did sprinkling become an
engineering term? Sounds very arbitrary to me > and it is.
Wouldn't change interplane resonances is any significant way.
> Where did this idea come
from? Is there supporting data?
>
> -----Original Message-----
> From: si-list-bounce@xxxxxxxxxxxxx
<si-list-bounce@xxxxxxxxxxxxx>
On Behalf
> Of Grasso, Charles
> Sent: Thursday, August 23, 2018
12:21 PM
> To: joel.brown@xxxxxxxxxx;
ken.patterson@xxxxxxxxxxxxxxxxx
> Cc: Lee Ritchey <leeritchey@xxxxxxxxxxxxx>; >
asparky@xxxxxxxxxxxxxxxxxxxxxxxx; Istvan Novak
<istvan.novak@xxxxxxxxxxx>; > junichi.yamada.ak@xxxxxxxxxxx; SI-List
<si-list@xxxxxxxxxxxxx> > Subject: [SI-LIST] Re: Controled ESR
capacitor > > I see two distinct applications.
The low inductance application is for > energy delivery. The cap
sprinkle (sorry Lee!) is to manage the interplane > resonances.
>
>
>
> -----Original Message-----
> From: si-list-bounce@xxxxxxxxxxxxx
[mailto:si-list-bounce@xxxxxxxxxxxxx]
On
> Behalf Of Joel Brown
> Sent: Thursday, August 23, 2018
10:47 AM
> To: ken.patterson@xxxxxxxxxxxxxxxxx > Cc: Lee Ritchey
<leeritchey@xxxxxxxxxxxxx>; > asparky@xxxxxxxxxxxxxxxxxxxxxxxx;
Istvan Novak <istvan.novak@xxxxxxxxxxx>; >
junichi.yamada.ak@xxxxxxxxxxx; SI-List <si-list@xxxxxxxxxxxxx> >
Subject: [SI-LIST] Re: Controled ESR capacitor > > This message
originated outside of DISH and was sent by:
> si-list-bounce@xxxxxxxxxxxxx
>
> In the book I previously mentioned
it clearly states the most important
> aspect of a bypass cap is mounting
inductance.
> Adding a discrete resistor in
series obviously adds a significant amount of > inductance.
> But since the PDN impedeance would
be flatter maybe the extra inductance can > be tolerated.
> Would be interesting to see the
trade offs between very low ESR with lowest > inductance and
resistor in series with capacitor.
>
> On Thu, Aug 23, 2018 at 8:58 AM,
Ken Patterson <
> ken.patterson@xxxxxxxxxxxxxxxxx>
wrote:
>
>> You have to wear a mask as to
not inhale them accidentally!
>> On Thu, Aug 23, 2018 at 11:56
AM <leeritchey@xxxxxxxxxxxxx>
wrote:
>>
>>> I can't even see 0201s!
>>>
>>> -----Original
Message-----
>>> From: si-list-bounce@xxxxxxxxxxxxx
<si-list-bounce@xxxxxxxxxxxxx> On >>> Behalf Of Aubrey Sparkman >>>
Sent: Wednesday, August 22, 2018 5:08 PM >>> To:
leeritchey@xxxxxxxxxxxxx >>> Cc: istvan.novak@xxxxxxxxxxx;
junichi.yamada.ak@xxxxxxxxxxx; >>> si-list@xxxxxxxxxxxxx >>>
Subject: [SI-LIST] Re:
Controled ESR capacitor
>>>
>>>
>>> Discontinue 0402s for
0201s...
>>>
>>> Consider using 0201s
instead of 0402s if you are doing a redesign >>> due to caps.
>>>
>>> Youre welcome!
:-)
>>>
>>> Aubrey
>>>
>>>
>>>
>>> Sent from my iPhone
>>>
>>>> On Aug 22, 2018, at
11:29 AM, <leeritchey@xxxxxxxxxxxxx>
<
>>> leeritchey@xxxxxxxxxxxxx>
wrote:
>>>> We just got informed
by our ceramic capacitor suppliers that they >>>> were >>>
discontinuing their 0603 sizes to focus on 0402 as that is where the
redesign several >>> PCBs >> to >>> the smaller size.action >>> is with cell phones and tablets. Going to make is
>>>> What next?
>>>>
>>>> -----Original
Message-----
>>>> From: si-list-bounce@xxxxxxxxxxxxx
<si-list-bounce@xxxxxxxxxxxxx> >>>> On Behalf Of Istvan Novak >>>>
Sent: Tuesday, August 21, 2018 8:30 PM >>>> To:
junichi.yamada.ak@xxxxxxxxxxx; si-list@xxxxxxxxxxxxx >>>> Subject:
[SI-LIST] Re:
Controled ESR capacitor
>>>>
>>>> Hi Yamada,
>>>>
>>>> This appears to be
part of a generic trend of component shortage >>>> and >>> product
cancellations:
ceramic capacitor manufacturers are rerouting >> their >>> existing
production capabilities to higher-volume and more lucrative >>>
applications. Users over the many years have been very successful
financially >>> not viable to invest in new manufacturing capacity.demanding lower prices to the point that it has become
The interesting >>> twist is that people try to replace ceramic
capacitors with other >>> types, for instance polymer capacitors,
which tend to be more costly > then ceramics.
>>> On a practical note: if
you need an ohm of ESR, you can simply add a >> series >>> one-ohm
discrete resistor. The added piece increases the >>> inductance,
but with an ESR of an ohm, the impact tends to be small.
>>> This of course wont help
if you already have a product in volume >>> manufacturing with just
the controlled-ESR footprint.
>>>> Regards,
>>>>
>>>> Istvan Novak
>>>>
>>>>
>>>>> On 8/21/2018 9:49
AM, Junichi Yamada wrote:
>>>>> Hello experts
>>>>> In my product, I
use ESR controlled capacitor. (For example ESR > >> 1000 >>>>> m)
However, TDK decided to discontinue this product.
>>>>>
https://product.tdk.com/info/en/products/emc/emc/absorber/catalog
>>>>> .htm
>>>>> l
>>>>>
>>>>>
>>>>> Please let me know
if you know another capacitor with similar >>> characteristics.
>>>>> * I know the
Murata's LLR series. (However, there is the >>>>> possibility of
discontinuing production as well.) >>>>>
https://psearch.en.murata.com/capacitor/product/LLR185C70G105ME07%23.
>>>>> h
>>>>> tml
>>>>>
>>>>> Regards.
>>>>> Yamada
>>>>>
>>>>>
>>>>>
-----------------------------------------------------------------
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>>> --
>> Ken Patterson
>> *Senior Hardware Engineer*
>> *The Telos Alliance *
>> *1241 Superior Ave*
>>
>> *Cleveland, Ohio 44144*
>> Main: +1.216.241.7225
<javascript:void(0);>
>> 24/7 Support:
+1.216.622.0247 <javascript:void(0);> >> [image:
www.telosalliance.com] <http://telosalliance.com/> >>
<https://www.facebook.com/TelosAlliance> <https://twitter.com/ ;>>
TelosAlliance> >> <https://www.linkedin.com/company/telosalliance>
>> <https://www.youtube.com/user/TelosAllianceTV>
>>
>>
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Warm Regards,
Binayak Shrestha
Senior Research Engineer,
C-DOT Centre for Development of Telematics
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List archives are viewable at:
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