Your clarification makes me even more puzzled about your conclusions. If this
is general one die core noise to clock tree buffer power, why would you
sacrifice the critical >100MHz noise damping that most core logic will care for
the 30MHz or so that most switching logic don't care ? Is your chip only
working in 30-40MHz ?
Back to the PLL jitter issue. As long as the clock buffer output is used for
the PLL phase detector input, it is still part of the closed PLL controlled
loop. You can see below 20MHz the PLL loop bandwidth corrected the induced
jitter on the clock tree buffer. You just luck out that when the reduced cap
configuration peaked around 10MHz, that was below the PLL loop bandwidth. Had
the PLL loop bandwidth is forced to be lowered by crazy PLL spec like PCIE to
5MHz, the 10MHz peaking of the red curve will most probably be higher than the
high cap count configuration peak around 35MHz.
Sorry, these are important design trade-offs that I am not sure you have drawn
the right conclusion. We should keep this discussion going.
Chris Cheng
Distinguished Technologist , Electrical
Hewlett-Packard Enterprise Company
+1 510 344 4439/ Tel
chris.cheng@xxxxxxx / Email
940 N. McCarthy Blvd., Milpitas, CA 95035
USA
From: Iliya Zamek [mailto:i_zamek@xxxxxxxxx] ;
Sent: Wednesday, August 29, 2018 1:28 PM
To: Cheng, Chris <chris.cheng@xxxxxxx>
Cc: dmarc-noreply@xxxxxxxxxxxxx; binayaks@xxxxxxxxx <binayaks@xxxxxxxxx>;
tom@xxxxxxxxxxxxxxxxx; si-list@xxxxxxxxxxxxx <si-list@xxxxxxxxxxxxx>; FRED
MOTTER <motter@xxxxxxxxxxxxx>; FRED B <FRED@xxxxxxxxxxxxx>; Jacques Tazartes
<jacquest15@xxxxxxxxxxxxx>; EmadIbrahim <EIbrahim@xxxxxxxxx>;
Myrna5@xxxxxxxxxxxxxx <Myrna5@xxxxxxxxxxxxxx>; Istvan Novak
<istvan.novak@xxxxxxxxxxx>; junichi.yamada.ak@xxxxxxxxxxx
<junichi.yamada.ak@xxxxxxxxxxx>; Cosmin Iorga <ci42775@xxxxxxxxx>
Subject: Re: [SI-LIST] Re: Controlled ESR capacitor
Hi Chris,
Thank you for your comments.
Both, 30-40 and 100-200 MHz jitter
components are important. There is no
point to sacrifice one, or other.
This was special experiment to validate
the role of board decoupling on
interaction of two logic domains inside
the chip which shared the same
power supply: core logic was switching
(Aggressor) impacting routing
component's and clock tree' jitter (victims).
PLL on clock tree was using other, quiet
power supply. Scale is the same as on
figure 4: (jitter at core switching)/(jitter
at core quiet).
Let me know if you have more questions.
Thank you.
Iliya
On Aug 29, 2018 11:10 AM, "Cheng, Chris" <chris.cheng@xxxxxxx> wrote:
Why do you think it is worth sacrificing the 100-200MHz jitter performance with
high cap count for the narrow range of 30-40MHz jitter performance with lower
cap count ?
In the world of XbitY coding for the 10+Gb/s world, I would think the
100-200Mhz jitter performance is much more important than those 30-40MHz.
To me, the best conclusion I can draw from the two graph seems to point out the
price we pay for the obsession of jitter transfer over jitter accumulation.
Clearly the 30-40Mhz jitter peaking could be fixed by uping the PLL loop
bandwidth from around 10MHz to 40+MHz. In the name of saving a few $ in cheap
clock source, we paid this price for all PLL jitter accumulation downstream.
To recap :
a) Who would feed a PLL with raw unfiltered power and rely on decoupling cap
ESR to maintain PLL jitter performance ?
b) Why is it worth sacrificing 100-200MHz jitter performance to a lower band
30-40MHz ?
Also, what was the vertical scale of the graphs ?
Chris Cheng
Distinguished Technologist , Electrical
Hewlett-Packard Enterprise Company
+1 510 344 4439/ Tel
chris.cheng@xxxxxxx / Email
940 N. McCarthy Blvd., Milpitas, CA 95035
USA
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On ;
Behalf Of Iliya Zamek
Sent: Monday, August 27, 2018 8:39 PM
To: binayaks@xxxxxxxxx
Cc: dmarc-noreply@xxxxxxxxxxxxx; Cheng, Chris <chris.cheng@xxxxxxx>;
tom@xxxxxxxxxxxxxxxxx; si-list@xxxxxxxxxxxxx; FRED MOTTER
<motter@xxxxxxxxxxxxx>; FRED B <FRED@xxxxxxxxxxxxx>; Jacques Tazartes
<jacquest15@xxxxxxxxxxxxx>; EmadIbrahim <EIbrahim@xxxxxxxxx>;
Myrna5@xxxxxxxxxxxxxx; Istvan Novak <istvan.novak@xxxxxxxxxxx>;
junichi.yamada.ak@xxxxxxxxxxx; Cosmin Iorga <ci42775@xxxxxxxxx>
Subject: [SI-LIST] Re: Controlled ESR capacitor
Somehow my email was distorted. Re-sending.
Hi Binayak,
Your effect description is correct.
If you look at papers which links were included in my email sent 2 days ago
(August 25) you can see the graph that described exactly the same - how low
PCB impedance causes rising on-die transients.
If you could not find these papers, you might connect me off-line and I'll send
it to you.
Thank you.
Iliya.
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