[SI-LIST] Re: CPLD getting blown on board
- From: "Stefan Milnor" <stefan.milnor@xxxxxxxxxxxxxx>
- To: <austin@xxxxxxxxxx>, <hsiuanju@xxxxxxxxxxx>, <weirsi@xxxxxxxxxx>, "SI-list freelist" <si-list@xxxxxxxxxxxxx>
- Date: Fri, 7 Jun 2013 11:35:54 -0700
That's my thought as well - is there anything driving the CPLD pins
before the CPLD rails are up?
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
On Behalf Of austin@xxxxxxxxxx
Sent: Friday, June 07, 2013 11:26 AM
To: hsiuanju@xxxxxxxxxxx; weirsi@xxxxxxxxxx; 'SI-list freelist'
Subject: [SI-LIST] Re: CPLD getting blown on board
Hi All,
Possible CMOS Latch-up?
Check this:
http://www.analog.com/library/analogDialogue/archives/35-05/latchup/
Best regards,
Austin
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
On Behalf Of Hsiuan-ju Hsu
Sent: Friday, June 07, 2013 9:31 AM
To: weirsi@xxxxxxxxxx; SI-list freelist
Subject: [SI-LIST] Re: CPLD getting blown on board
Hi, Sam,
I had experience about the shut-down last year.
Please follow up the previous suggestions from SI experts and do the
last thing here:
Do Power Integrity simulation for 3.3V core first, then 2.5V. Make sure
the Ztarget is less than 5% below 10MHz.
I think it should help.
Best regards,
Robert Hsu
> Date: Fri, 7 Jun 2013 08:06:28 -0700
> From: weirsi@xxxxxxxxxx
> To: si-list@xxxxxxxxxxxxx
> Subject: [SI-LIST] Re: CPLD getting blown on board
>
> One more item to list to the many good suggestions offered: Make sure
> that you don't have a power sequencing problem during shut-down as
> well as power on. As it is during power up / power down your device
> fails, I would go after the power sequencing, VRM overshoot first.
>
> Steve.
> On 6/7/2013 5:38 AM, Sam Pete wrote:
> > Hi Friends,
> > I am working on a medical board which has multi-core CPU along with
other peripherals.
> > we are getting into some issue that CPLD is getting blown out during
power cycle or sometimes during reset.
> > out of 210 boards we produced, we have 3 boards exhibiting this
issue.
The FA report from CPLD vendor says electrical over-stress...
> > The board is not having any hotswap peripherals.... CPLD has 2.5V
> > and
3.3V banks, 3.3V Core/IO supply comes up first then 2.5V.
> > We have gone thru all sorts of checks, negative tests etc., to
> > reproduce
this issue and we were unsuccessful....
> > Does anybody faced similar issues earlier? Appreciate if you can
> > provide
some clues...
> >
> > thanks
> > Sam
> >
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