[SI-LIST] Re: CPLD getting blown on board

  • From: "Orin Laney" <olaney@xxxxxxxxx>
  • To: <cygnul@xxxxxxxxx>, <si-list@xxxxxxxxxxxxx>
  • Date: Fri, 7 Jun 2013 15:13:23 -0400

Standard practice for many PDN designs is to put a power diode between
supplies to the same part, with the cathode on the higher voltage supply so
that the diode is normally off.  If the lower voltage supply comes up before
the higher voltage supply, they will stay within a diode drop of each other.
If the higher supply turns off more rapidly, the same result applies.  For
most parts, if the reverse voltage disparity is not more than a PN diode
drop no damage results.  Use schottky to guarantee that clamping happens at
lower voltage than would turn on the IC protection networks.  It's good
cheap insurance, also protects against sudden shorts on the higher line.
I've seen too many cases of regulator turn-on overshoot and other power
sequencing anomalies to try to save the 5 cents for the diode.

Orin Laney

-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On
Behalf Of Sam Pete
Sent: Friday, June 07, 2013 8:38 AM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] CPLD getting blown on board

Hi Friends,
I am working on a medical board which has multi-core CPU along with other
peripherals.
we are getting into some issue that CPLD is getting blown out during power
cycle or sometimes during reset.
out of 210 boards we produced, we have 3 boards exhibiting this issue. The
FA report from CPLD vendor says electrical over-stress...
The board is not having any hotswap peripherals.... CPLD has 2.5V and 3.3V
banks, 3.3V Core/IO supply comes up first then 2.5V.
We have gone thru all sorts of checks, negative tests etc., to reproduce
this issue and we were unsuccessful.... Does anybody faced similar issues
earlier? Appreciate if you can provide some clues...

thanks
Sam

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