[SI-LIST] Re: CPLD getting blown on board

  • From: "Istvan Nagy" <buenos@xxxxxxxxxxx>
  • To: <dhwn@xxxxxxx>, <cygnul@xxxxxxxxx>
  • Date: Fri, 7 Jun 2013 08:48:46 -0700

Hi,

One more thing that I would add:
Sometimes people don't implement a few already connected signals in the CPLD 
code, then the synthesizer makes them by default output-drive-low. To avoid 
this, set a synthesizer setting "unused pins" = "input tri-stated".

regards,
Istvan Nagy
Fortinet

-----Original Message----- 
From: Donald Nelson
Sent: Friday, June 07, 2013 6:37 AM
To: cygnul@xxxxxxxxx
Cc: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: CPLD getting blown on board

Hi Sam, A few items to check:
1) Check the power rails as they ramp up to their correct voltages; do they 
overshoot? Do they settle within the DC specifications of the CPLD? Do they 
have ripple that exceeds spec (checked continuously from powerup to full 
load)?

2) Are there power sequencing requirements for the CPLD (or other parts) 
that are not being met? (have you verified on a scope that 3.3V is first, 
followed by 2.5V?)

3) Is the CPLD receiving data inputs from other devices before its own rails 
have ramped up (can forward bias the input protection diodes)

4) Are all signals terminated properly?

5) Are all signal voltage levels correct for the I/O banks? 5V signal into a 
2.5V I/O bank on the CPLD, for instance.

6) Have the power supplies been properly qualified for loop stability? 
Do they strongly overshoot during step-increases in load?

7) Is your CPLD pinout correct? For instance, is an output accidentally 
connected to an output from another device?

8) In fact, check your CPLD pinout again: are all of the power pins 
connected properly to the correct rails?

9) Have you verified all of your Gozintas and your Gozoutas for the CPLD? 
All what you expect? ("Gozinta" = "Goes Into", "Gozouta" = "Goes Out of" for 
you younger guys :-)

Good Luck,
-Don
Alcatel-Lucent

--
Don Nelson

"The whole problem with the world is that fools and fanatics are so sure of 
themselves, and wiser people so full of doubt" --Bertrand Russell


On Jun 07, 2013, at 08:49 AM, Scott McMorrow <scott@xxxxxxxxxxxxx> wrote:

> Sam
> Look for excessive overshoot/undershoot on the signal lines received by 
> the
> CPLD.
>
> regards,
>
> Scott
>
>
> On Fri, Jun 7, 2013 at 8:38 AM, Sam Pete <cygnul@xxxxxxxxx> wrote:
>
> > Hi Friends,
> > I am working on a medical board which has multi-core CPU along with 
> > other
> > peripherals.
> > we are getting into some issue that CPLD is getting blown out during 
> > power
> > cycle or sometimes during reset.
> > out of 210 boards we produced, we have 3 boards exhibiting this issue. 
> > The
> > FA report from CPLD vendor says electrical over-stress...
> > The board is not having any hotswap peripherals.... CPLD has 2.5V and 
> > 3.3V
> > banks, 3.3V Core/IO supply comes up first then 2.5V.
> > We have gone thru all sorts of checks, negative tests etc., to reproduce
> > this issue and we were unsuccessful....
> > Does anybody faced similar issues earlier? Appreciate if you can provide
> > some clues...
> >
> > thanks
> > Sam
> >
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> -- 
>
> Scott McMorrow
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