[SI-LIST] Re: Article discussion on bad packages - core
- From: "Jeremy Plunkett" <jeremy@xxxxxxxxxxxxxxx>
- To: weirsp@xxxxxxxxxx, "'Istvan NOVAK'" <istvan.novak@xxxxxxxxxxxxxxxx>
- Date: Sat, 8 Jan 2005 01:10:41 -0800
Hmmm...hate to expose myself reading SI list this late on a Friday =
night,
but I have to point out that if Istvan is using blind vias he can =
probably
place them in a row under the part between the two pads, alternating VDD =
GND
VDD GND and get pretty much the lowest inductance possible for a cap =
with 2
terminals connecting to buried planes.
On the other hand if these are caps on the bottom of a PCB under a BGA
pinfield, probably the best way to go is make the bottom layer (outer, =
2+
mils thick after plating) VDD and the next one up GND, in which case =
you'd
put the blind vias in the GND pad and improve your mounted inductance =
even
further. =20
Actually Istvan, I'm curious how much you end up gaining with the blind =
vias
in this situation, since you'll need through-hole vias to get the power =
up
to the processor on the other side of the board anyway. These thru vias
should already be all over the place in a VDD/GND checkerboard, is it =
really
worth removing any of them to place pads for 0306's and microvias, when =
you
could just pack the area with 0402's placed between the thru vias and =
cut
the plane spreading inductance out of the picture completely?=20
Regards,
Jeremy
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] =
On
Behalf Of steve weir
Sent: Thursday, January 06, 2005 8:04 PM
To: Istvan NOVAK
Cc: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: Article discussion on bad packages - core
At 10:59 PM 1/6/2005 -0500, Istvan NOVAK wrote:
>Steve,
>
> > > > At the
> > > > capacitor attachment to the planes, it also tends to close at=20
> > > > about
>70 -
> > >75
> > > > degrees versus a virtual 90 degrees for the big "V" that I=20
> > > > prefer.
> > >
> > >I may miss here something; do you refer to the phase of impedance=20
> > >of the lumped parallel capacitors at a fixed, say 100MHz?
> >
> > Yes, if we look at the phase for the network at the capacitor=20
> > attachment ring ( really rings for a beast with 400 some odd caps ), =
> > it varies from -90degrees at low frequency to +90 degrees well above =
> > the close. We had been discussing that it is desirable to cross the =
> > package cut-off near 0 degrees which it is if it were feasible to do =
> > at little or no additonal cost. The issue is feasibility. I don't=20
> > know of a way to get there without adding a monstrous quantity of=20
> > additional caps. If you have a
>way,
> > you have me beat.
>
>In your second example below (X^2.2 method, 429 capacitors, 858 vias,=20
>73 deg. closing phase), do you look at the phase at 100MHz? What is=20
>the highest SRF of the smallest-value capacitor?
Yes, that is correct. The mounted SRF was 76MHz for the smallest=20
capacitance in the X2Y group.
> >
> > > > Big "V" in conventional caps: 800pH / mounted cap / 1.6pH=20
> > > > budget =3D
>500
> > > > capacitors, 1000 vias, 90 deg. closing phase.
> > > >
> > > > X^2.2 method, 429 capacitors, 858 vias, 73 deg. closing phase.
> > > >
> > > > Big "V" in low inductance caps: 200pH / mounted cap ( 6 via=20
> > > > X2Y, or 8
>via
> > > > IDC ), 126 low L caps, + 3 10uF conventional caps to cover the=20
> > > > low
>end,
> > >129
> > > > caps total, 762 vias, 90 deg closing phase.
> > > >
> > > > X^2.2 method variant using a combination of low inductance and
> > >conventional
> > > > caps, 84 low inductance, + 42 conventional caps again for the=20
> > > > low end,
>126
> > > > caps total, 588 vias, 70 degrees closing phase at 100MHz.
> > >
> > >The above options are possible, but you could continue the list for =
> > >instance with another implementation of the big "V" with 'regular'=20
> > >low-inductance capacitors. 0508 or 0306 parts with four=20
> > >through-hole vias give you 200-300pH and a microfarad capacitance=20
> > >minimum per piece. 125 caps of the 200pH kind with only 4*125=3D500 =
> > >vias total give you the 1.6pH inductance you need and more than=20
> > >100uF capacitance, so you
>dont
> > >need
> > >10uF ceramics.
> >
> > Well, the devil is in what the actual numbers really are. 200pH to=20
> > 300pH is quite a wide relative spread. 125 pcs. at 200pH would just=20
> > do it, but 300pH would require 185 parts, and more like 740 vias. =20
> > The capacitance needed to reach down to 1MHz is 160uF. The big "V"=20
> > case listed above was 126X1uF + 3x10uF. It looks like for your=20
> > 200pH case that is still required, whereas in the 300pH it is not. =20
> > The good news for the 200pH
>case
> > is that with 126X1uF caps, there will not be a problem with an AR=20
> > peak transitioning from the 10uF caps.
> >
>
>Agree that 200-300pH is a large range, moreover if we want to compare=20
>inductance numbers for the same part in various applications, layout=20
>and stackup details will also matter. I am curious: next to126*1uF=20
>caps, did you find the 3*10uF parts being useful?
Well, if we neglect the extra 30uF, the model shows we blow target |Z| =
by=20
about 20% at the low-end. So to avoid any specmanship, I built the =
models=20
to meet the spec in each configuration, end to end.
> > > >
> > > > Now, as much as I am not very happy about the number of=20
> > > > different
> > >capacitor
> > > > values required by the X^2.2 method or variations on it,=20
> > > > removing 23%
>of
> > > > the vias is something that could prove quite compelling to an=20
> > > > OEM.
> > >
> > >This depends on the technology we use. If we use blind vias to=20
> > >hook up capacitors, and the planes we connect to are the second and =
> > >third layers below the surface, we can hook up both sides of the=20
> > >capacitors with blind vias. Blind vias in pads are perfectly safe=20
> > >today, you dont even need to plug them. Blind vias add some extra=20
> > >cost, BUT 1) you do not block any routing layers further inside the =
> > >stackup, so this is even better than any of the options
> > >listed above, and 2) when you compare the area needed for one =
capacitor
>with
> > >through-hole connection versus blind-vias-in-pad connection, the=20
> > >cost reduction because of the savings in board area will eventually =
> > >make many applications with blind vias cheaper.
> >
> > Well, you may find a number of people who object to the cost of a=20
> > blind
>via
> > process. In a high-end product like a server, that may be moot, =
and I
> > fully concede that as a component that needs that qty of bypass caps =
> > will have other demanding requirments that may well prove that the=20
> > lowest cost component, or process, does not yield the lowest cost=20
> > assembly. I think this needs to be evaluated on a case by case=20
> > basis. But you do raise a very worthwhile point.
>
>Absolutely agree, it depends on the industry segment.
>
> >
> > I am unclear as to why you seem to conclude that blind vias are=20
> > restricted to either conventional capacitors, or the big "V"=20
> > configuration. If we
>are
> > willing to use blind vias, we can see inductance gains with=20
> > conventional, reverse geometry, X2Y, or IDC capacitor attachments=20
> > and gain against component count needed at the high frequency end=20
> > whether we go with big
>"V"
> > or x^2.2.
> >
>I did not mean to conclude that blind vias are restricted to certain=20
>kind of capacitors, and I agree that a 'better' via arrangement can=20
>further improve onb the inductance
>of low-inductance capacitors as well. Note that the 200-300pH =
inductance
>values for
>the above example was with standard four-via connections.
I think that is a good point. Now, let's suppose 200pH is the right =
number=20
for the 0306s. Larry's x^2.2 method would still be perfectly valid and=20
should reduce the number of capacitors needed by about 20%, but of =
course=20
with the caveats that approach carries.
The data that I have collected on 0306 w/ 4 vias has never matched, nor=20
bested X2Y 0603 with 6 vias. The useful FOM I think is whether the X2Y =
w/=20
6 vias comes out at 0.67 or less the mounted inductance of an 0306 for =
any=20
particular situation that we wish to consider. I presume that you are=20
placing your vias off the long axis ends as Jeremy has repeatedly =
suggested.
Regards,
Steve
>Best regards,
>
>Istvan Novak
>SUN Microsystems
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