[SI-LIST] Re: Article discussion on bad packages - core
- From: steve weir <weirsp@xxxxxxxxxx>
- To: Larry.Smith@xxxxxxx, twesterh@xxxxxxxxx
- Date: Tue, 04 Jan 2005 15:29:48 -0800
Larry, I agree on the desirability of presenting low phase angle from the
PCB to the IC package near the package LPF cut-off to hold down
Q. However, as I have looked at the problem with my feeble brain, I keep
coming up with monstrous capacitor counts, and only conditional solutions.
Are you seeing good success holding the phase angle of the PCB w/mounted
bypass caps below say 45 degrees at the package LPF cut-off using the
closely-spaced SRF technique or a variation on it at 1-10 milliohm
impedances? If so, maybe I will try and screw my brain into this notion
and see if I take a better liking to the caveats that I never favored with
that approach.
I assume you are relying on the combined capacitor bank ESR, and plane
spreading resistance at the cut-off for the resistive loss. Is that right?
When I run the numbers with available caps, there are only some impedance
configurations that I find any decent solutions for owing to the fixed
relationship of resistance to capacitance in a given package / chemistry /
voltage, and the fixed inductance of a given package. Do you find similarly?
If so, I am thinking that we should be looking at alternatives to effect
the damping in the package and allow the capacitor network to get by with
the big "V". I do have a couple of ideas.
Regards,
Steve.
At 11:37 AM 1/4/2005 -0800, Larry SMITH wrote:
>Todd - Your comments are right on target! I've been sorting through all
>my email after a nice long break and there has been a lot of energy on
>this thread. One of the confusion factors is that we are getting SSN
>and I/O return current mixed up with core power transients (VDD/Gnd).
>These are two very different PI topics and need to be considered in very
>different ways. I want to make some further remarks to your comments
>on the core PDS. As you have implied, the correct approach is to
>examine the individual components (chip, package, PCB) and combine them
>into a power distribution system.
>
>1) On-die decoupling capacitance is very important because it is the
>only charge reservoir that is going to supply current above
>approximately 100MHz to a system that has a target impedance of
>approximately 1 mOhm. 1.59pH is 1 mOhm at 100MHz and it is nearly
>impossible reduce the package inductance to that realm. The chip must
>be self sufficient above some frequency, approximately 100 MHz. Our
>recent micro processors have had on-chip decoupling capacitance on the
>order of 500nF, which is 3.18mOhms at 100 MHz, so we have chosen the
>dividing line at about the right frequency.
>
>The best way to find the on-chip capacitance is to measure it. I have
>not seen a software tool yet that can correctly predict the whole chip
>capacitance. Measure the capacitance of a bare PCB using a VNA and then
>attach the chip and remeasure. The capacitance of the chip is the
>difference between the two measurements. Be sure and bias the chip at
>the proper voltage. In my experience, the capacitance of the chip goes
>up about 3X with bias because of all the FET channels are formed by gate
>bias. The chip comes up in a completely unknown state but I don't
>believe the chip capacitance is a strong state function. The gates that
>are not switching form capacitance for those that are.
>
>The on-chip capacitance forms a parallel LC circuit with the package
>inductance and PCB impedance and makes a PDS peak that I call
>chip/package resonance. It is the most difficult impedance peak in the
>PDS. I have not seen a system yet that meets target impedance in this
>frequency band, but they seem to keep working anyway, probably because
>the circuits can tolerate more voltage drop than we thought.
>
>2) On-package capacitance can help this situation, but the challenge is
>to hook it up with conductors that are less than the target impedance.
>Very Difficult! One strategy is to take the core power solder bumps
>straight down to the PCB pins with package vias. In this case,
>on-package capacitance must be off to the side. It is very difficult to
>mount capacitors on the package and channel their current into the core
>power solder bumps with 1 mOhm or less of series impedance at 100 MHz.
>Package power planes suffer from the same spreading inductance and
>perforation degradation as PCB power planes.
>
>Another strategy is to place the on-package capacitors directly
>underneath the chip core and connect them with 100's of package vias.
>This makes the on-package capacitors effective but now you have to bring
>in ~100 amps of DC current on package power planes that are probably
>perforated. Hmmm. There is really no good way to do it and this may be
>the very motivation behind the EE Times article and the subject of this
>thread.
>
>The decisions made by the package designer pretty much determine the
>quality of the PDS that the circuits on the chip see as they look for
>gobs of current at low impedance. It is certainly possible to make a
>mistake on-chip or on-pcb, but the electronic package is probably the
>most critical part of the core PDS design. To a great extent, the pin
>pitch of the package influences the spreading inductance of the
>perforated PCB power planes that bring power to the core power pins. If
>the core power pins are surrounded by many rows of I/O pins on 1
>millimeter pitch, there will be precious little copper left between the
>PCB antipads to channel the current. High resistance and high
>inductance! If there are 1000's of I/O, the PCB will have to be thick
>to escape all the signals, which drives up the via and antipad size,
>further compounding the problem. This is just another example of
>decisions made by the package designer affecting the PDS quality of the
>system by forcing constraints on the PCB power planes. The package
>design can truly make or break the system design.
>
>3) Your question (proposal) pertains to documenting a chip's high speed
>power requirements. Let's further clarify it to be a "packaged chip"
>because a corner frequency has already been set by the chip/package
>resonant frequency. The PCB designer is responsible for keeping the PDS
>impedance below the target up to the corner frequency that is
>established by chip/package resonance. The "breakout" portion of the
>PCB should be considered to be part of the package because it's design
>dimesions have been set by the package. The impedance of the broad PCB
>should be resistive rather than inductive at the chip/package resonant
>frequency because that lowers the Q of the resonant circuit (inductance
>raises the Q).
>
>The most crucial piece of information from the chip manufacturer is the
>maximum and minimum currents that can be drawn from the PCB PDS. This
>establishes the dI or transient current that the PCB must supply. The
>rise time (dt) is determined by the low pass filter associated with the
>chip/package resonant frequency. Generally, customer code will
>determine the current waveform and therefor the frequency profile of the
>current drawn by the chip, so I don't believe it is fair to ask chip
>vendors for the power spectrum. However, they should be obligated to
>give their customers the maximum and minimum current that their chip
>will ever draw. The minium I is probably determined by sleep mode and
>power saving states.
>
>There is a move a foot to standardize the tools and methods used for
>power integrity. This is a very worthwhile endeavor. But it is a huge
>problem and must be broken down into solvable parts. This note pertains
>to core power and transient current on Vdd and Gnd. The SSN and return
>current PI problem is entirely different. It will help if we divide
>these two problems and conquer them individually.
>
>regards,
>Larry Smith
>Sun Microsystems
>
>Todd Westerhoff (twesterh) wrote:
> > Happy New Year to all!
> >
> > Having gone through the collection of messages to this point, I have a few
> > questions I'd like to raise:
> >
> > 1) How are people accounting for the effects of on-die decoupling in their
> > analyses? We can analyze the power delivery capbilities of the
> package, but
> > part of the power delivery system is implemented by on-die decoupling,
> isn't
> > it? How do folks go about extracting die parasitics and incorporating them
> > into their PDS analyses?
> >
> > 2) It seems to me that the combination of on-die and [optionally]
> on-package
> > decoupling makes the package/die PDS self-sufficient above some frequency.
> > If we look at the board PDS, the target PDS impedance requirements would
> > therefore increase with frequency. The rolloff (or rollup, if you prefer)
> > of target impedance with frequency would be design-specific, and, I
> believe,
> > complex to determine, but would nonetheless serve as a design requirement
> > for the board's PDS at that point.
> >
> > My question here - does anyone else think this would be a possible and
> > reasonable method for documenting a chip's high speed current requirements?
> > I suggest we leave FPGAs out for the moment, since their requirements will
> > be design specific. Could we document PDS impedance/frequency profiles for
> > standard components, and use that information to segregate some of the high
> > speed signaling and PDS design tasks?
> >
> > Comments are welcome and appreciated.
> >
> > Todd.
> >
> > Todd Westerhoff
> > High Speed Design Specialist
> > Cisco Systems
> > 1414 Massachusetts Ave - Boxboro, MA - 01719
> > email:twesterh@xxxxxxxxx
> > ph: 978-936-2149
> > ============================================
> >
> > "Always do right.
> > This will gratify some people and astonish the rest."
> >
> > - Mark Twain
> >
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