[SI-LIST] Re: Article discussion on bad packages - core
- From: steve weir <weirsp@xxxxxxxxxx>
- To: "Istvan NOVAK" <istvan.novak@xxxxxxxxxxxxxxxx>
- Date: Thu, 06 Jan 2005 20:03:55 -0800
At 10:59 PM 1/6/2005 -0500, Istvan NOVAK wrote:
>Steve,
>
> > > > At the
> > > > capacitor attachment to the planes, it also tends to close at about
>70 -
> > >75
> > > > degrees versus a virtual 90 degrees for the big "V" that I prefer.
> > >
> > >I may miss here something; do you refer to the phase of impedance of
> > >the lumped parallel capacitors at a fixed, say 100MHz?
> >
> > Yes, if we look at the phase for the network at the capacitor attachment
> > ring ( really rings for a beast with 400 some odd caps ), it varies from
> > -90degrees at low frequency to +90 degrees well above the close. We had
> > been discussing that it is desirable to cross the package cut-off near 0
> > degrees which it is if it were feasible to do at little or no additonal
> > cost. The issue is feasibility. I don't know of a way to get there
> > without adding a monstrous quantity of additional caps. If you have a
>way,
> > you have me beat.
>
>In your second example below (X^2.2 method, 429 capacitors, 858 vias,
>73 deg. closing phase), do you look at the phase at 100MHz? What is
>the highest SRF of the smallest-value capacitor?
Yes, that is correct. The mounted SRF was 76MHz for the smallest
capacitance in the X2Y group.
> >
> > > > Big "V" in conventional caps: 800pH / mounted cap / 1.6pH budget =
>500
> > > > capacitors, 1000 vias, 90 deg. closing phase.
> > > >
> > > > X^2.2 method, 429 capacitors, 858 vias, 73 deg. closing phase.
> > > >
> > > > Big "V" in low inductance caps: 200pH / mounted cap ( 6 via X2Y, or 8
>via
> > > > IDC ), 126 low L caps, + 3 10uF conventional caps to cover the low
>end,
> > >129
> > > > caps total, 762 vias, 90 deg closing phase.
> > > >
> > > > X^2.2 method variant using a combination of low inductance and
> > >conventional
> > > > caps, 84 low inductance, + 42 conventional caps again for the low end,
>126
> > > > caps total, 588 vias, 70 degrees closing phase at 100MHz.
> > >
> > >The above options are possible, but you could continue the list
> > >for instance with another implementation of the big "V" with 'regular'
> > >low-inductance capacitors. 0508 or 0306 parts with four through-hole
> > >vias give you 200-300pH and a microfarad capacitance minimum per piece.
> > >125 caps of the 200pH kind with only 4*125=500 vias total give you
> > >the 1.6pH inductance you need and more than 100uF capacitance, so you
>dont
> > >need
> > >10uF ceramics.
> >
> > Well, the devil is in what the actual numbers really are. 200pH to 300pH
> > is quite a wide relative spread. 125 pcs. at 200pH would just do it, but
> > 300pH would require 185 parts, and more like 740 vias. The capacitance
> > needed to reach down to 1MHz is 160uF. The big "V" case listed above was
> > 126X1uF + 3x10uF. It looks like for your 200pH case that is still
> > required, whereas in the 300pH it is not. The good news for the 200pH
>case
> > is that with 126X1uF caps, there will not be a problem with an AR peak
> > transitioning from the 10uF caps.
> >
>
>Agree that 200-300pH is a large range, moreover if we want to compare
>inductance numbers for the same part in various applications, layout and
>stackup details will also matter. I am curious: next to126*1uF caps,
>did you find the 3*10uF parts being useful?
Well, if we neglect the extra 30uF, the model shows we blow target |Z| by
about 20% at the low-end. So to avoid any specmanship, I built the models
to meet the spec in each configuration, end to end.
> > > >
> > > > Now, as much as I am not very happy about the number of different
> > >capacitor
> > > > values required by the X^2.2 method or variations on it, removing 23%
>of
> > > > the vias is something that could prove quite compelling to an OEM.
> > >
> > >This depends on the technology we use. If we use blind vias to hook up
> > >capacitors, and the planes we connect to are the second and third layers
> > >below the surface, we can hook up both sides of the capacitors with blind
> > >vias. Blind vias in pads are perfectly safe today, you dont even need to
> > >plug them. Blind vias add some extra cost, BUT 1) you do not block any
> > >routing
> > >layers further inside the stackup, so this is even better than any of the
> > >options
> > >listed above, and 2) when you compare the area needed for one capacitor
>with
> > >through-hole connection versus blind-vias-in-pad connection, the cost
> > >reduction because of the savings in board area will eventually make many
> > >applications with blind vias cheaper.
> >
> > Well, you may find a number of people who object to the cost of a blind
>via
> > process. In a high-end product like a server, that may be moot, and I
> > fully concede that as a component that needs that qty of bypass caps will
> > have other demanding requirments that may well prove that the lowest cost
> > component, or process, does not yield the lowest cost assembly. I think
> > this needs to be evaluated on a case by case basis. But you do raise a
> > very worthwhile point.
>
>Absolutely agree, it depends on the industry segment.
>
> >
> > I am unclear as to why you seem to conclude that blind vias are restricted
> > to either conventional capacitors, or the big "V" configuration. If we
>are
> > willing to use blind vias, we can see inductance gains with conventional,
> > reverse geometry, X2Y, or IDC capacitor attachments and gain against
> > component count needed at the high frequency end whether we go with big
>"V"
> > or x^2.2.
> >
>I did not mean to conclude that blind vias are restricted to certain kind of
>capacitors,
>and I agree that a 'better' via arrangement can further improve onb the
>inductance
>of low-inductance capacitors as well. Note that the 200-300pH inductance
>values for
>the above example was with standard four-via connections.
I think that is a good point. Now, let's suppose 200pH is the right number
for the 0306s. Larry's x^2.2 method would still be perfectly valid and
should reduce the number of capacitors needed by about 20%, but of course
with the caveats that approach carries.
The data that I have collected on 0306 w/ 4 vias has never matched, nor
bested X2Y 0603 with 6 vias. The useful FOM I think is whether the X2Y w/
6 vias comes out at 0.67 or less the mounted inductance of an 0306 for any
particular situation that we wish to consider. I presume that you are
placing your vias off the long axis ends as Jeremy has repeatedly suggested.
Regards,
Steve
>Best regards,
>
>Istvan Novak
>SUN Microsystems
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