[SI-LIST] Re: Article discussion on bad packages - core
- From: "Istvan NOVAK" <istvan.novak@xxxxxxxxxxxxxxxx>
- To: "steve weir" <weirsp@xxxxxxxxxx>, <larry.smith@xxxxxxx>
- Date: Thu, 6 Jan 2005 21:55:58 -0500
Steve,
> At the
> capacitor attachment to the planes, it also tends to close at about 70 -
75
> degrees versus a virtual 90 degrees for the big "V" that I prefer.
I may miss here something; do you refer to the phase of impedance of
the lumped parallel capacitors at a fixed, say 100MHz?
> Big "V" in conventional caps: 800pH / mounted cap / 1.6pH budget = 500
> capacitors, 1000 vias, 90 deg. closing phase.
>
> X^2.2 method, 429 capacitors, 858 vias, 73 deg. closing phase.
>
> Big "V" in low inductance caps: 200pH / mounted cap ( 6 via X2Y, or 8 via
> IDC ), 126 low L caps, + 3 10uF conventional caps to cover the low end,
129
> caps total, 762 vias, 90 deg closing phase.
>
> X^2.2 method variant using a combination of low inductance and
conventional
> caps, 84 low inductance, + 42 conventional caps again for the low end, 126
> caps total, 588 vias, 70 degrees closing phase at 100MHz.
The above options are possible, but you could continue the list
for instance with another implementation of the big "V" with 'regular'
low-inductance capacitors. 0508 or 0306 parts with four through-hole
vias give you 200-300pH and a microfarad capacitance minimum per piece.
125 caps of the 200pH kind with only 4*125=500 vias total give you
the 1.6pH inductance you need and more than 100uF capacitance, so you dont
need
10uF ceramics.
>
> Now, as much as I am not very happy about the number of different
capacitor
> values required by the X^2.2 method or variations on it, removing 23% of
> the vias is something that could prove quite compelling to an OEM.
This depends on the technology we use. If we use blind vias to hook up
capacitors, and the planes we connect to are the second and third layers
below the surface, we can hook up both sides of the capacitors with blind
vias. Blind vias in pads are perfectly safe today, you dont even need to
plug them. Blind vias add some extra cost, BUT 1) you do not block any
routing
layers further inside the stackup, so this is even better than any of the
options
listed above, and 2) when you compare the area needed for one capacitor with
through-hole connection versus blind-vias-in-pad connection, the cost
reduction because of the savings in board area will eventually make many
applications with blind vias cheaper.
Regards,
Istvan Novak
SUN Microsystems
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