[SI-LIST] Re: Article discussion on bad packages - core
- From: Chris Cheng <Chris.Cheng@xxxxxxxxxxxx>
- To:
- Date: Wed, 5 Jan 2005 13:58:14 -0800
Steve,
I am going to give you some answers you may not like, but that's reality.
Who says the current path for the I/O and I/O power/ground has to be the
same as the core power and its return on the PCB ? I have the dubious
reputation of working on some of the highest power processors modules (not
necessary the highest speed) and a lot of them do not share the same
connection point at the module.
While we almost draw the exact conclusions in our processor power
distribution studies with Larry. I have to add that whoever win the war on
I/O bandwidth per pin also takes the spoils of having an easier path on
running the current through that gauntlet of mesh. And also, does a 100W
3GHz processor necessary has 100W of 10MHz noise in the first place ? While
it is possible to pump specific test vector to excite the core power to
generate noise big enough to hit the package resonance or below, it will be
extremely difficult to replicate that in real system with real application
software. I am not trying to give excuses but that's the reality. The issue
is how much real 10-100MHz switching current you are expecting to see.
That's a very difficult call that many Principal/Distinguish engineers in
those CPU house will make in a dark smoke fill room, BTDT.
The good news is what Larry is describing is typical high performance
processor power distribution not typical ASIC or FPGA silicons which has
significant less di/dt. After all, how many ASIC out there is >100W (big di)
and really running >1GHz at core (not I/O) (small dt) and there are not that
many processor companies left and typically they have either a captive
market (use only in their in house system) or they have a majority of their
customers following a well defined reference design which they can well
analyze in advanced with detail modeling from die through package to PCB.
Remember my comment about don't be cute and go off the beaten path ? I have
worked on both and you simply address the problem differently. In the former
case you have absolute control and the later you pray your customer follow
your reference design and don't stray away. I don't believe there is really
a clean cut case where you can analyze the individual section on its own, at
least not for high speed high power processors. However, you can model
individual sections with vastly different level of complexity, from complex
clock buffer/ff/metal mesh on die to 2 D grids on package to 1D ladder
models on PCB.
Good point to clearly state that this is a core power distribution
discussion and not related to SSO noise analysis.
Finally, to Ray and fellow lister,
My deep apology for the previous message. Those comments should have been
offline where it will be easily confirmed. And as it turns out my old gang
in SUN has invited me for dinner tonight so I think the remarks and
confirmation will remain private there.
Regards,
Chris
-----Original Message-----
From: steve weir [mailto:weirsp@xxxxxxxxxx]
Sent: Wednesday, January 05, 2005 12:01 PM
To: Larry.Smith@xxxxxxx
Cc: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: Article discussion on bad packages - core
Larry, thanks for the detailed response. At 10MHz, yes low phase angles
are quite feasible, but at 100MHz, well, at this juncture I have trouble
summoning that kind of magic. Even with thin dielectrics close to the
mounting surface, and an arbitrary number of attachment vias, the spreading
inductance always seem to be the show-stopper..
Suppose for example we synthesize a perfectly resistive mounted capacitor
array as viewed at a ring of some radius R2 on the planes, and have such an
arbitrary number of package attachment vias that we can neglect their
contribution. Off hand, with conventional caps and closely spaced SRFs I
believe we are still talking well over 100 capacitors. Then just from the
spreading inductance to hold 45 degrees phase we get:
3 mil dielectric R2/R1 ( where R1 is the mean power pin radius ) would have
to be a likely impossible 1.1.
0.63 mil C-Ply ( as aggressive as I think anyone can presently get ) would
have to be 1.4 which is still anything but easy, and is going to rely on
some very thin not too badly perforated planes in the BGA.
But the conversation does have me pondering an idea or two on how we could
do better with what is currently available. And admittedly, 45 degrees or
even 70 degrees will still be better than 85 degrees.
Are you using antipads significantly smaller than 30 mils? If you could
get away with even 25 mils that would help a lot.
That's interesting that you are getting such a high ESR for 100nF
caps. Most of the data I have places them at about 20mohms from multiple
manufacturers in X7R/X5R. Are you using some really small capacitor
packages?
I am familiar with the transmission line models that you guys developed as
more accurate than the lumped models. that's an interesting refinement. I
am sure that does help avoid an unnecessarily pessimistic model.
I don't envy your task of finding a way to get 1mohm at 100MHz. But maybe
it gives you the opportunity to play with some fun stuff.
BTW, have you done any tolerancing work to examine how far beyond the
package cut-off you need to hold phase? Without having run specific
numbers, my feel for it is that 2X should be enough to stay out of trouble.
Thanks again for the detailed reply.
Regards,
Steve.
At 11:09 AM 1/5/2005 -0800, Larry SMITH wrote:
>Steve - The key to getting a resistive impedance profile up into the
>10's of MHz on the PCB is the use of low inductance mounts for the
>capacitors. Larger value capacitors have lower ESR than small value
>capacitors so you need fewer of them to reach a target impedance. By
>using low inductance mounts you help yourself in several ways:
>
>- the series resonant frequency is higher which makes the capacitor
>effective at higher frequency;
>- the Q is lower so the dip is broader and holds the impedance down over
>a larger frequency range;
>- the capacitor internal inductance is reduced and the ESR is increased
>at frequencies beyond series resonances.
>
>I choose capacitors from a menu of X5R and X7R dielectrics with three
>values per decade: 0.1uF, 0.22, 0.47, 1, 2.2, 4.7, ... My
>characterization shows that a 0.1uF cap has about 30 mOhms of ESR and
>resonates at about 20 MHz when mounted on 300pH pads. 30 of them in
>parallel get you to 1 mOhm. But you really don't need that many if you
>have properly chosen and mounted the higher value caps because their ESR
>is still helping you at 20MHz. I use "transmission line" spice models
>for the caps that correctly predict the inductance and ESR at
>frequencies above series resonance, and this helps a lot. The impedance
>vs frequency profile of a ceramic cap is not a symmetrical V if you
>mount it on low enough inductance pads. My models are documented in
>papers on the SI-list web site. I'll be presenting these concepts again
>at DesignCon in a few weeks.
>
>The PCB power plane spreading inductance begins to really hurt you above
>about 20 MHz when you are trying to hit that 1 mOhm target. Thin power
>plane dielectrics are one of the few things that can help. Otherwise,
>you need to put some capacitance on the package or directly under the
>chip.
>
>I would be interested in the alternative solutions that you mentioned in
>this area.
>
>regards,
>Larry Smith
>Sun Microsystems
>
>steve weir wrote:
> > Larry, I agree on the desirability of presenting low phase angle from
the
> > PCB to the IC package near the package LPF cut-off to hold down
> > Q. However, as I have looked at the problem with my feeble brain, I
keep
> > coming up with monstrous capacitor counts, and only conditional
solutions.
> >
> > Are you seeing good success holding the phase angle of the PCB w/mounted
> > bypass caps below say 45 degrees at the package LPF cut-off using the
> > closely-spaced SRF technique or a variation on it at 1-10 milliohm
> > impedances? If so, maybe I will try and screw my brain into this
notion
> > and see if I take a better liking to the caveats that I never favored
with
> > that approach.
> >
> > I assume you are relying on the combined capacitor bank ESR, and plane
> > spreading resistance at the cut-off for the resistive loss. Is that
right?
> >
> > When I run the numbers with available caps, there are only some
impedance
> > configurations that I find any decent solutions for owing to the fixed
> > relationship of resistance to capacitance in a given package / chemistry
/
> > voltage, and the fixed inductance of a given package. Do you find
> similarly?
> >
> > If so, I am thinking that we should be looking at alternatives to effect
> > the damping in the package and allow the capacitor network to get by
with
> > the big "V". I do have a couple of ideas.
> >
> > Regards,
> >
> >
> > Steve.
> >
> >
> >
> > At 11:37 AM 1/4/2005 -0800, Larry SMITH wrote:
> >
> >>Todd - Your comments are right on target! I've been sorting through all
> >>my email after a nice long break and there has been a lot of energy on
> >>this thread. One of the confusion factors is that we are getting SSN
> >>and I/O return current mixed up with core power transients (VDD/Gnd).
> >>These are two very different PI topics and need to be considered in very
> >>different ways. I want to make some further remarks to your comments
> >>on the core PDS. As you have implied, the correct approach is to
> >>examine the individual components (chip, package, PCB) and combine them
> >>into a power distribution system.
> >>
> >>1) On-die decoupling capacitance is very important because it is the
> >>only charge reservoir that is going to supply current above
> >>approximately 100MHz to a system that has a target impedance of
> >>approximately 1 mOhm. 1.59pH is 1 mOhm at 100MHz and it is nearly
> >>impossible reduce the package inductance to that realm. The chip must
> >>be self sufficient above some frequency, approximately 100 MHz. Our
> >>recent micro processors have had on-chip decoupling capacitance on the
> >>order of 500nF, which is 3.18mOhms at 100 MHz, so we have chosen the
> >>dividing line at about the right frequency.
> >>
> >>The best way to find the on-chip capacitance is to measure it. I have
> >>not seen a software tool yet that can correctly predict the whole chip
> >>capacitance. Measure the capacitance of a bare PCB using a VNA and then
> >>attach the chip and remeasure. The capacitance of the chip is the
> >>difference between the two measurements. Be sure and bias the chip at
> >>the proper voltage. In my experience, the capacitance of the chip goes
> >>up about 3X with bias because of all the FET channels are formed by gate
> >>bias. The chip comes up in a completely unknown state but I don't
> >>believe the chip capacitance is a strong state function. The gates that
> >>are not switching form capacitance for those that are.
> >>
> >>The on-chip capacitance forms a parallel LC circuit with the package
> >>inductance and PCB impedance and makes a PDS peak that I call
> >>chip/package resonance. It is the most difficult impedance peak in the
> >>PDS. I have not seen a system yet that meets target impedance in this
> >>frequency band, but they seem to keep working anyway, probably because
> >>the circuits can tolerate more voltage drop than we thought.
> >>
> >>2) On-package capacitance can help this situation, but the challenge is
> >>to hook it up with conductors that are less than the target impedance.
> >>Very Difficult! One strategy is to take the core power solder bumps
> >>straight down to the PCB pins with package vias. In this case,
> >>on-package capacitance must be off to the side. It is very difficult to
> >>mount capacitors on the package and channel their current into the core
> >>power solder bumps with 1 mOhm or less of series impedance at 100 MHz.
> >>Package power planes suffer from the same spreading inductance and
> >>perforation degradation as PCB power planes.
> >>
> >>Another strategy is to place the on-package capacitors directly
> >>underneath the chip core and connect them with 100's of package vias.
> >>This makes the on-package capacitors effective but now you have to bring
> >>in ~100 amps of DC current on package power planes that are probably
> >>perforated. Hmmm. There is really no good way to do it and this may be
> >>the very motivation behind the EE Times article and the subject of this
> >>thread.
> >>
> >>The decisions made by the package designer pretty much determine the
> >>quality of the PDS that the circuits on the chip see as they look for
> >>gobs of current at low impedance. It is certainly possible to make a
> >>mistake on-chip or on-pcb, but the electronic package is probably the
> >>most critical part of the core PDS design. To a great extent, the pin
> >>pitch of the package influences the spreading inductance of the
> >>perforated PCB power planes that bring power to the core power pins. If
> >>the core power pins are surrounded by many rows of I/O pins on 1
> >>millimeter pitch, there will be precious little copper left between the
> >>PCB antipads to channel the current. High resistance and high
> >>inductance! If there are 1000's of I/O, the PCB will have to be thick
> >>to escape all the signals, which drives up the via and antipad size,
> >>further compounding the problem. This is just another example of
> >>decisions made by the package designer affecting the PDS quality of the
> >>system by forcing constraints on the PCB power planes. The package
> >>design can truly make or break the system design.
> >>
> >>3) Your question (proposal) pertains to documenting a chip's high speed
> >>power requirements. Let's further clarify it to be a "packaged chip"
> >>because a corner frequency has already been set by the chip/package
> >>resonant frequency. The PCB designer is responsible for keeping the PDS
> >>impedance below the target up to the corner frequency that is
> >>established by chip/package resonance. The "breakout" portion of the
> >>PCB should be considered to be part of the package because it's design
> >>dimesions have been set by the package. The impedance of the broad PCB
> >>should be resistive rather than inductive at the chip/package resonant
> >>frequency because that lowers the Q of the resonant circuit (inductance
> >>raises the Q).
> >>
> >>The most crucial piece of information from the chip manufacturer is the
> >>maximum and minimum currents that can be drawn from the PCB PDS. This
> >>establishes the dI or transient current that the PCB must supply. The
> >>rise time (dt) is determined by the low pass filter associated with the
> >>chip/package resonant frequency. Generally, customer code will
> >>determine the current waveform and therefor the frequency profile of the
> >>current drawn by the chip, so I don't believe it is fair to ask chip
> >>vendors for the power spectrum. However, they should be obligated to
> >>give their customers the maximum and minimum current that their chip
> >>will ever draw. The minium I is probably determined by sleep mode and
> >>power saving states.
> >>
> >>There is a move a foot to standardize the tools and methods used for
> >>power integrity. This is a very worthwhile endeavor. But it is a huge
> >>problem and must be broken down into solvable parts. This note pertains
> >>to core power and transient current on Vdd and Gnd. The SSN and return
> >>current PI problem is entirely different. It will help if we divide
> >>these two problems and conquer them individually.
> >>
> >>regards,
> >>Larry Smith
> >>Sun Microsystems
> >>
> >>Todd Westerhoff (twesterh) wrote:
> >>
> >>>Happy New Year to all!
> >>>
> >>>Having gone through the collection of messages to this point, I have a
few
> >>>questions I'd like to raise:
> >>>
> >>>1) How are people accounting for the effects of on-die decoupling in
their
> >>>analyses? We can analyze the power delivery capbilities of the
> >>
> >>package, but
> >>
> >>>part of the power delivery system is implemented by on-die decoupling,
> >>
> >>isn't
> >>
> >>>it? How do folks go about extracting die parasitics and incorporating
> them
> >>>into their PDS analyses?
> >>>
> >>>2) It seems to me that the combination of on-die and [optionally]
> >>
> >>on-package
> >>
> >>>decoupling makes the package/die PDS self-sufficient above some
frequency.
> >>>If we look at the board PDS, the target PDS impedance requirements
would
> >>>therefore increase with frequency. The rolloff (or rollup, if you
prefer)
> >>>of target impedance with frequency would be design-specific, and, I
> >>
> >>believe,
> >>
> >>>complex to determine, but would nonetheless serve as a design
requirement
> >>>for the board's PDS at that point.
> >>>
> >>>My question here - does anyone else think this would be a possible and
> >>>reasonable method for documenting a chip's high speed current
> requirements?
> >>>I suggest we leave FPGAs out for the moment, since their requirements
will
> >>>be design specific. Could we document PDS impedance/frequency
> profiles for
> >>>standard components, and use that information to segregate some of the
> high
> >>>speed signaling and PDS design tasks?
> >>>
> >>>Comments are welcome and appreciated.
> >>>
> >>>Todd.
> >>>
> >>>Todd Westerhoff
> >>>High Speed Design Specialist
> >>>Cisco Systems
> >>>1414 Massachusetts Ave - Boxboro, MA - 01719
> >>>email:twesterh@xxxxxxxxx
> >>>ph: 978-936-2149
> >>>============================================
> >>>
> >>>"Always do right.
> >>> This will gratify some people and astonish the rest."
> >>>
> >>>- Mark Twain
> >>>
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