[SI-LIST] Re: Why Termination at Both End ?
- From: Peter.Pupalaikis@xxxxxxxxxx
- To: si-list@xxxxxxxxxxxxx
- Date: Wed, 24 Aug 2011 03:03:27 -0400
Steve's comments reminded me of a situation we were discussing about a chip
design the other day. That is, if you do have an imperfect (or purposely
bad) termination at the receiver end (like a high-impedance), then try not
to evaluate any performance by looking at the waveform at the source - it
may look horrible and in the case of a clock, it is possible that the
voltage waveform is nearly non-existent, while the waveform at the receive
end looks fine. We ran into this recently in a slightly embarrassing
situation.
Also, these types of cases are really probing nightmares (if you're doing
that sort of thing) when you cannot probe right at the receiver and it
becomes very difficult to interpret the results.
Pete
From: steve weir <weirsi@xxxxxxxxxx>
To: si-list@xxxxxxxxxxxxx
Date: 08/24/2011 01:51 AM
Subject: [SI-LIST] Re: Why Termination at Both End ?
Sent by: si-list-bounce@xxxxxxxxxxxxx
Sen, for electrically long lines, that topology introduces about 13% -
14% ISI. Arrange an electrical length that happens to be close to half
of one phase interval and the ISI will step right onto the incident edge
of your timing strobe which is boo hiss bad stuff.
I am not saying that there are never places where you would want to
compromise this way. If you don't have the amplitude to spare
termination at both ends then its something you can do, provided you do
the rest of the homework to make sure you don't get yourself into
trouble. In that spirit, I would recommend only applying a band-aid
like this where one either is absolutely certain from the back of the
envelope that ISI won't be a problem, or one takes the time to simulate.
Steve.
On 8/23/2011 4:07 PM, Sen Velmurugan wrote:
> Steve,
> Here the buffer is a current source, the termination(pulldown) is the
> load, the high input impedance receiver see the voltage across the load.
> The foot print at destination does offer some(pf) capacitance. These
> layouts are done in the absence of simulations and to clean up
mismatches.
> Usually done for clock and analog video signals.
> Thanks
> Sen
>
>
>> Msg: #2 in digest
>> Date: Mon, 22 Aug 2011 16:55:47 -0700
>> From: steve weir<weirsi@xxxxxxxxxx>
>> Subject: [SI-LIST] Re: Why Termination at Both End ?
>>
>> Sen, are you suggesting this:
>>
>> Tx side: Isink || (Pull-up = 2*Zline) --> Tx Line ---> (Pull-up =
>> 2*Zline) Rx side
>>
>> In this case you are mismatched at both sides and you will have ISI due
>> to reflections.
>>
>> If you have an RLL signal stream, from an ISI point of view you would be
>> better off with:
>>
>> Tx side: Isink || (Pull-up = Zline) --> Tx Line ---> ( R=Zline --> C
>> --> Vss ) || Receiver
>>
>> Where RC> 5X the maximum run length.
>>
>> Steve
>>
>> On 8/22/2011 4:17 PM, Sen Velmurugan wrote:
>>
>>> Rajan, When you need Xohm termination to sink a current source, you can
>>> use 2Xohm termination each at source and destination.
>>> This way source see, 2X || 2X = X ohm sink and voltage at load is
>>> "cleaner". Basically, you have more freedom of choice to play with.
>>>
>>> ~Sen.Velmurugan@xxxxxxxxxx
>>>
>>>
>>>
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