[SI-LIST] Re: Why Termination at Both End ?

  • From: Hermann Ruckerbauer <hermann.ruckerbauer@xxxxxxxxxxxxx>
  • To: Rajan Hansa <all.si.list@xxxxxxxxx>
  • Date: Fri, 12 Aug 2011 13:46:20 +0200

Hello,
sorry for beeing late on this one ..
I have asked as similar question as well when having seen a Source +
load termination on a PCIe clock buffer from ICS/IDT.
Here the information I got from IDT:

The 9DB106 outputs are switched constant current sources.  The output
cannot sink current.  The 49.9 ohm resistors are needed to sink current
and pull the signal lines low.  Double termination is not normally
recommended.  The reference designs you see using the 9DB106 should only
have termination at the source.  In some cases it needs to be at the
load.  For example some PCIe devices have internal 50 ohm termination to
ground.  In this case it is okay - just remove the termination at the
source if it is a motherboard down design.  The problem is add-in in
boards that use a PCIe device with internal termination to ground.  The
ASIC vendor needs to correct their designs to be compatible with the
PCI-SIG PCIe standard if it is being used on an add-in board.

So my interpretation of this answer was, that the main reason for the
source termination is the HSCL constant current output buffer. Without
any defined sink current capability a reflection might not be
terminated, but reflected. 
But I'm not sure if my interpretation of the answer was correct ...
But based on this i think when asking this question it is requried to
define the interface that is used ..


Hermann

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Hermann Ruckerbauer
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schrieb Rajan Hansa:
> Experts,
>
> Can anyone explain that why in some designs we see source as well as load
> terminations, I mean termination at both side of traces ?  If ringing is a
> issue then only source termination should be sufficient to control it and we
> can use a receiver with very high input impedance i.e. no need to match
> input impedance of receiver with transmission line characteristics
> impedance.
>
> Rajan
>
>
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