[SI-LIST] Re: Why Termination at Both End ?
- From: "alfred1520list" <alfred1520list@xxxxxxxxx>
- To: <si-list@xxxxxxxxxxxxx>
- Date: Wed, 24 Aug 2011 09:40:08 -0700
----- Original Message -----
From: <Peter.Pupalaikis@xxxxxxxxxx>
Sent: Wednesday, August 24, 2011 12:03 AM
> Steve's comments reminded me of a situation we were discussing about a chip
> design the other day. That is, if you do have an imperfect (or purposely
> bad) termination at the receiver end (like a high-impedance), then try not
> to evaluate any performance by looking at the waveform at the source - it
> may look horrible and in the case of a clock, it is possible that the
> voltage waveform is nearly non-existent, while the waveform at the receive
> end looks fine.
I can attest to this. It happened on a pretty mundane situation. I thought
I'll
share so some one like myself a few years ago would benefit.
We have a 148.5 MHz video clock driving a relatively long trace, around 10"
long,
that's in the inner layer. As usual we only source series terminate it. So
when
we have some video problems, we look at the clock line. Since we don't have
easy access to the end of the line, we looked at the down stream side of the
series termination resistor, THERE IS NO CLOCK, just a
constant DC line with a little
bit of noise. How could it have ever worked? After some series head scratching
and pondering, we realized this is exactly the situation that Peter described.
Looking from the RF antenna engineering point of view, this should be
obvious. When the transmission line is exactly 1/4 the wave length, it becomes
a 1/4 wave transformer that transforms the open circuit at the far end to a
short
at the near end, hence the flat line. DC is not affected by the transformer so
you
see only the DC average of the waveform.
Best Regards,
Alfred Lee
http://www.mds.com
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