[SI-LIST] Re: Why Termination at Both End ?

Howard Johnson has a nice analysis on dual series termination: 
http://www.sigcon.com/Pubs/news/2_20.htm

Best Regards
Charles Grasso
Compliance Engineer
Echostar Communications
(w) 303-706-5467
(c) 303-204-2974
(t) 3032042974@xxxxxxxxx
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(e2) chasgrasso@xxxxxxxxx


-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On 
Behalf Of steve weir
Sent: Friday, August 12, 2011 6:47 AM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: Why Termination at Both End ?

Hermann, IDT is recommending against termination on both ends because it 
will attenuate the signal swing unacceptably.  This is the same problem 
that plagued rail-to-rail signal CMOS and TTL/LVTTL standards.  The 
price that one pays for using those standards is much tighter impedance 
control requirements on the PCB and the terminators.

With a 49.9 Ohm sink resistor, the current source looks like a 49.9 Ohm 
source.  If the resistor is placed at the far end, then the device looks 
like a very high impedance with an end termination of 49.9 Ohms.  In 
that case any reflection from far-end mismatch such as caused by 
parasitic capacitance or trace impedance error travels back up to the 
clock buffer and bounces right off of it.

Steve.


On 8/12/2011 4:46 AM, Hermann Ruckerbauer wrote:
> Hello,
> sorry for beeing late on this one ..
> I have asked as similar question as well when having seen a Source +
> load termination on a PCIe clock buffer from ICS/IDT.
> Here the information I got from IDT:
>
> The 9DB106 outputs are switched constant current sources.  The output
> cannot sink current.  The 49.9 ohm resistors are needed to sink current
> and pull the signal lines low.  Double termination is not normally
> recommended.  The reference designs you see using the 9DB106 should only
> have termination at the source.  In some cases it needs to be at the
> load.  For example some PCIe devices have internal 50 ohm termination to
> ground.  In this case it is okay - just remove the termination at the
> source if it is a motherboard down design.  The problem is add-in in
> boards that use a PCIe device with internal termination to ground.  The
> ASIC vendor needs to correct their designs to be compatible with the
> PCI-SIG PCIe standard if it is being used on an add-in board.
>
> So my interpretation of this answer was, that the main reason for the
> source termination is the HSCL constant current output buffer. Without
> any defined sink current capability a reflection might not be
> terminated, but reflected.
> But I'm not sure if my interpretation of the answer was correct ...
> But based on this i think when asking this question it is requried to
> define the interface that is used ..
>
>
> Hermann
>
> EKH - EyeKnowHow
> Hermann Ruckerbauer
> www.EyeKnowHow.de
> Hermann.Ruckerbauer@xxxxxxxxxxxxx
> Veilchenstrasse 1
> 94554 Moos
> Tel.: +49 (0)9938 / 902 083
> Mobile: +49 (0)176 / 787 787 77
> Fax: +49 (0)3212 / 121 9008
>
> schrieb Rajan Hansa:
>> Experts,
>>
>> Can anyone explain that why in some designs we see source as well as load
>> terminations, I mean termination at both side of traces ?  If ringing is a
>> issue then only source termination should be sufficient to control it and we
>> can use a receiver with very high input impedance i.e. no need to match
>> input impedance of receiver with transmission line characteristics
>> impedance.
>>
>> Rajan
>>
>>
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-- 
Steve Weir
IPBLOX, LLC
150 N. Center St. #211
Reno, NV  89501
www.ipblox.com

(775) 299-4236 Business
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