[SI-LIST] Re: Overshoot / Undershoot
- From: Bill.Cohen@xxxxxxxxxxxxxxxx
- To: andrew.seddon@xxxxxxxxxxxx
- Date: Thu, 12 Jan 2006 19:45:03 -0500
Andrew,
JEDEC has an overshoot/undershoot specification for DDR2 a 1.8V technology.
Older technologies relied on an absolute voltage but the newer technologies
work on an absolute maximum and an area (above/below power) of stress. This
area limits the overshoot stress into a maximum stress for a period of
time. The long time reliability of the gate oxide is at issue here and the
duty cycle of the signal also comes into play. Look at the DDR2 datasheet
(JEDEC.org) and look at the stress model they have for undershoot/overshoot
of input signals. We have incorporated this model into our latest
specifications.
Best Regards,
--------------------------------------------------------------
| Bill Cohen
| Toshiba America Electronic Components
| Mixed Signal Design Group
--------------------------------------------------------------
"Andrew Seddon"
<andrew.seddon@ca
msig.co.uk> To
Sent by: <si-list@xxxxxxxxxxxxx>
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Subject
[SI-LIST] Overshoot / Undershoot
01/12/2006 07:30
PM
Please respond to
andrew.seddon@cam
sig.co.uk
Hello,
I was wondering if anybody had an idea of what is a typically acceptable
bad
but workable overshoot/undershoot on a 3.3V system? For example I see some
memory IC's can take transients upto 5.5v where as the datasheet max is say
+0.3. Obviously this figure is based on DC.
I presume the major effect's of over/under shoot are to reduce working life
of the IC and make the circuit potentially fail at temperature extremes?
So when you guys analyse overshoot/undershoot how do you decide if it's
acceptable?
Kind regards,
Andrew
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