Posts for si-list, 01-2006

Browse: Last Month: 12-2005 Main Archive Page Next Month: 02-2006

» [SI-LIST] Boston Area Job Opening -
» [SI-LIST] SPI 2006 - Deadline Extension -
» [SI-LIST] Re: Opinions wanted on Signal Integrity analysis tools -
» [SI-LIST] Re: Opinions wanted on Signal Integrity analysis tools -
» [SI-LIST] Re: differential impedance -
» [SI-LIST] Re: Opinions wanted on Signal Integrity analysis tools -
» [SI-LIST] Re: Opinions wanted on Signal Integrity analysis tools -
» [SI-LIST] Re: Opinions wanted on Signal Integrity analysis tools -
» [SI-LIST] Re: Opinions wanted on Signal Integrity analysis tools -
» [SI-LIST] Opinions wanted on Signal Integrity analysis tools -
» [SI-LIST] differential impedance -
» [SI-LIST] Ethernet standards coding and data frequency -
» [SI-LIST] cml specifications -
» [SI-LIST] test -
» [SI-LIST] Short term consulting -
» [SI-LIST] What makes a good technical course/seminar? -
» [SI-LIST] Signal Integrity Engineer position-Intel Corporation, Chandler, AZ -
» [SI-LIST] Re: test -
» [SI-LIST] Job Opening at Intel Santa Clara, CA. -
» [SI-LIST] Re: -3dB at S21 graph -
» [SI-LIST] Re: Capacitance -
» [SI-LIST] Re: Capacitance -
» [SI-LIST] Capacitance -
» [SI-LIST] Re: -3dB at S21 graph -
» [SI-LIST] Re: -3dB at S21 graph -
» [SI-LIST] -3dB at S21 graph -
» [SI-LIST] test -
» [SI-LIST] Spice measurements -
» [SI-LIST] SI Job Posting Optimal Corporation -
» [SI-LIST] Re: Best device model to learn SI -
» [SI-LIST] Re: Best device model to learn SI -
» [SI-LIST] Best device model to learn SI -
» [SI-LIST] It's Just a Small Design Change! -
» [SI-LIST] Re: Overshoot / Undershoot -
» [SI-LIST] Re: Decoupling Cap. Strategies. -
» [SI-LIST] Re: Decoupling Cap. Strategies. -
» [SI-LIST] Decoupling Cap. Strategies. -
» [SI-LIST] Rest mail Please ignore -
» [SI-LIST] Re: Overshoot / Undershoot -
» [SI-LIST] Re: Length matching on Gb lines -
» [SI-LIST] Re: Questions concerning DC-block Caps and coaxial optical packages ( ROSA/TOSA) -
» [SI-LIST] Re: Series termination greater than the characteristic impedance? -
» [SI-LIST] Re: Series termination greater than the characteristic impedance? -
» [SI-LIST] Questions concerning DC-block Caps and coaxial optical packages ( ROSA/TOSA) -
» [SI-LIST] Re: Series termination greater than the characteristic impedance? -
» [SI-LIST] Re: Length matching on Gb lines -
» [SI-LIST] Re: Length matching on Gb lines -
» [SI-LIST] Length matching on Gb lines -
» [SI-LIST] Re: Series termination greater than the characteristic impedance? -
» [SI-LIST] Re: si-list Digest V6 #14 -
» [SI-LIST] Re: si-list Digest V6 #14 -
» [SI-LIST] Multiple SI/characterization engineer positions at Altera (San Jose, CA) -
» [SI-LIST] Re: Series termination greater than the characteristic impedance? -
» [SI-LIST] Re: Series termination greater than the characteristic impedance? -
» [SI-LIST] Re: Length of Discontinuity -
» [SI-LIST] Length of Discontinuity -
» [SI-LIST] Series termination greater than the characteristic impedance? -
» [SI-LIST] Re: Eye diagram -
» [SI-LIST] Re: Eye diagram -
» [SI-LIST] Re: Eye diagram -
» [SI-LIST] Reflection around threshold point -
» [SI-LIST] Re: Overshoot / Undershoot -
» [SI-LIST] Re: Eye diagram -
» [SI-LIST] Re: Loop Inductance -
» [SI-LIST] Eye diagram -
» [SI-LIST] Buffer placement -
» [SI-LIST] Loop Inductance -
» [SI-LIST] Re: Overshoot / Undershoot -
» [SI-LIST] SPI 2006 - Call for Papers -
» [SI-LIST] Re: How to use S-parameter accurately -
» [SI-LIST] Engineering Influence -
» [SI-LIST] Re： Can anyone send me the BCM5466SR IBIS model -
» [SI-LIST] How to use S-parameter accurately -
» [SI-LIST] Re: Can anyone send me the BCM5466SR IBIS model -
» [SI-LIST] Can anyone send me the BCM5466SR IBIS model -
» [SI-LIST] Re: [Bulk] Re: PCB Impedance Failure -
» [SI-LIST] Introduction to Microelectronics Packaging course at San Jose State -
» [SI-LIST] Re: Overshoot / Undershoot -
» [SI-LIST] Re: [Bulk] Re: PCB Impedance Failure -
» [SI-LIST] Re: Overshoot / Undershoot -
» [SI-LIST] Re: Overshoot / Undershoot -
» [SI-LIST] Re: Overshoot / Undershoot -
» [SI-LIST] Immediate Signal Integrity Engineer Opening at Xilinx Inc. San Jose -
» [SI-LIST] Re: Overshoot / Undershoot -
» [SI-LIST] Re: Overshoot / Undershoot -
» [SI-LIST] Re: Overshoot / Undershoot -
» [SI-LIST] Re: Overshoot / Undershoot -
» [SI-LIST] SI Modeling Tutorial/Survey at PCI SIG DevCon-Europe and DesignCon 2006 -
» [SI-LIST] Re: Heat Dissipation Factor -
» [SI-LIST] Re: Overshoot / Undershoot -
» [SI-LIST] Re: OT: RoHS and Lead -
» [SI-LIST] Re: OT: RoHS and Lead -
» [SI-LIST] Re: differential pairs on backplane connectors -
» [SI-LIST] Re: Overshoot / Undershoot -
» [SI-LIST] Re: Overshoot / Undershoot -
» [SI-LIST] Overshoot / Undershoot -
» [SI-LIST] OT: RoHS and Lead -
» [SI-LIST] Re: [Bulk] Re: PCB Impedance Failure -
» [SI-LIST] Re: [Bulk] Re: PCB Impedance Failure -
» [SI-LIST] Part 2So You Want to be a Consultant -
» [SI-LIST] Heat Dissipation Factor -
» [SI-LIST] Re: preferred math package? (summary) -
» [SI-LIST] Quick analysis of a branched nets -
» [SI-LIST] Re: [Bulk] Re: PCB Impedance Failure -
» [SI-LIST] unsubscribe -
» [SI-LIST] Re: [Bulk] Re: PCB Impedance Failure -
» [SI-LIST] Re: METASTABILITY -
» [SI-LIST] EMI/EMC Test -
» [SI-LIST] Re: PCB Impedance Failure -
» [SI-LIST] ASIC Pinout / Package -
» [SI-LIST] Re: preferred math package? (summary) -
» [SI-LIST] Re: PCB Impedance Failure -
» [SI-LIST] Re: preferred math package? (summary) -
» [SI-LIST] Re: PCB Impedance Failure -
» [SI-LIST] Re: PCB Impedance Failure -
» [SI-LIST] Re: PCB Impedance Failure -
» [SI-LIST] PCB Impedance Failure -
» [SI-LIST] Re: 6 Layer microvia stackup -
» [SI-LIST] Update on Pulse Research Lab clock divider sample -
» [SI-LIST] Re： Inter Symbol Interference (ISI). -
» [SI-LIST] Re: 6 Layer microvia stackup -
» [SI-LIST] 6 Layer microvia stackup -
» [SI-LIST] Re: METASTABILITY -
» [SI-LIST] Opening for experienced SI engineer in San Diego -
» [SI-LIST] Re: METASTABILITY -
» [SI-LIST] Re: preferred math package? (summary) -
» [SI-LIST] Job Posting - Amphenol Corp, Sidney, NY -
» [SI-LIST] Inter Symbol Interference (ISI). -
» [SI-LIST] Inter Symbol Interference (ISI) -
» [SI-LIST] Inter Symbol Interference -
» [SI-LIST] Re: preferred math package? (summary) -
» [SI-LIST] Re: METASTABILITY -
» [SI-LIST] SI Job posting Vancouver BC Canada PMC-Sierra -
» [SI-LIST] EMCS-SCV Chapter Meeting, Tuesday January 10, 2006 -
» [SI-LIST] Re: So you want to be a consultant -
» [SI-LIST] Re: Maximum frequency consideration for high-speed digital analysis of differential signals -
» [SI-LIST] Re: METASTABILITY -
» [SI-LIST] Re: METASTABILITY -
» [SI-LIST] Re: METASTABILITY -
» [SI-LIST] Re: METASTABILITY -
» [SI-LIST] Re: METASTABILITY -
» [SI-LIST] An si-list meeting at DesignCon 2006 -
» [SI-LIST] Re: Maximum frequency consideration for high-speed digital analysis of differential signals -
» [SI-LIST] Re: Maximum frequency consideration for high-speed digital analysis of differential signals -
» [SI-LIST] Re: Maximum frequency consideration for high-speed digital analysis of differential signals -
» [SI-LIST] Re: Maximum frequency consideration for high-speed digital analysis of differential signals -
» [SI-LIST] about ibis model validation -
» [SI-LIST] Re: Maximum frequency consideration for high-speed digital analysis of differential signals -
» [SI-LIST] Re: si-list Digest V6 #4 -
» [SI-LIST] Re: si-list Digest V6 #4 -
» [SI-LIST] Re: So you want to be a consultant -
» [SI-LIST] Re: si-list Digest V6 #4 -
» [SI-LIST] So you want to be a consultant -
» [SI-LIST] Re: METASTABILITY -
» [SI-LIST] preferred math package? -
» [SI-LIST] Re: METASTABILITY -
» [SI-LIST] IBIS in PSpice -
» [SI-LIST] Re: METASTABILITY -
» [SI-LIST] Re: si-list Digest V6 #4 -
» [SI-LIST] Re: Maximum frequency consideration for high-speed digital analysis of differential signals -
» [SI-LIST] Re: Maximum frequency consideration for high-speed digital analysis of differential signals -
» [SI-LIST] Re: Maximum frequency consideration for high-speed digital analysis of differential signals -
» [SI-LIST] Re: Maximum frequency consideration for high-speed digital analysis of differential signals -
» [SI-LIST] Re: Maximum frequency consideration for high-speed digital analysis of differential signals -
» [SI-LIST] Re: Maximum frequency consideration for high-speed digital analysis of differential signals -
» [SI-LIST] Re: Maximum frequency consideration for high-speed digital analysis of differential signals -
» [SI-LIST] Re: METASTABILITY -
» [SI-LIST] Application different between Bus Switch and Bus Transceiver -
» [SI-LIST] Re: METASTABILITY -
» [SI-LIST] Re: METASTABILITY -
» [SI-LIST] Re: how to model frequency dependent resistor using hspice? -
» [SI-LIST] Re: Maximum frequency consideration for high-speed digital analysis of differential signals -
» [SI-LIST] Re: Maximum frequency consideration for high-speed digital analysis of differential signals -
» [SI-LIST] Re: METASTABILITY -
» [SI-LIST] Re: METASTABILITY -
» [SI-LIST] Maximum frequency consideration for high-speed digital analysis o f differential signals -
» [SI-LIST] Re: IBIS modelling in PSpice -
» [SI-LIST] FW: Re: FW: IBIS modelling in PSpice -
» [SI-LIST] small changes, big effects -
» [SI-LIST] Re: differential pairs on backplane connectors -
» [SI-LIST] Re: METASTABILITY -
» [SI-LIST] Re: differential pairs on backplane connectors -
» [SI-LIST] Re: FW: IBIS modelling in PSpice -
» [SI-LIST] Re: FW: IBIS modelling in PSpice -
» [SI-LIST] Re: IBIS modelling in PSpice -
» [SI-LIST] Re: METASTABILITY -
» [SI-LIST] Re: FW: IBIS modelling in PSpice -
» [SI-LIST] Re: Type of Driver -
» [SI-LIST] Re: METASTABILITY -
» [SI-LIST] Re: FW: IBIS modelling in PSpice -
» [SI-LIST] Re: METASTABILITY -
» [SI-LIST] Re: METASTABILITY -
» [SI-LIST] Re: Test PCB structures -
» [SI-LIST] Re: METASTABILITY -
» [SI-LIST] Re: FW: IBIS modelling in PSpice -
» [SI-LIST] Re: Test PCB structures -
» [SI-LIST] METASTABILITY -
» [SI-LIST] Re: XAUI -
» [SI-LIST] Re: Paksi-E Model Dielectric Constants -
» [SI-LIST] Re: XAUI -
» [SI-LIST] FW: IBIS modelling in PSpice -
» [SI-LIST] European IBIS Summit At DATe 2006 - Second Call for Paper/Call for Participation -
» [SI-LIST] differential pairs on backplane connectors -
» [SI-LIST] Type of Driver -
» [SI-LIST] Re: how to model frequency dependent resistor using hspice? -
» [SI-LIST] Re: Paksi-E Model Dielectric Constants -
» [SI-LIST] Paksi-E Model Dielectric Constants -
» [SI-LIST] Connector impedance mismatch -
» [SI-LIST] how to model frequency dependent resistor using hspice? -
» [SI-LIST] Re: IBIS modelling in PSpice -
» [SI-LIST] Re: IBIS modelling in PSpice -
» [SI-LIST] IBIS modelling in PSpice -
» [SI-LIST] SI Contract With Intel in Chandler, AZ -
» [SI-LIST] Re: PCI-X 1.0a simulation -
» [SI-LIST] SI Jobs in Austin, TX -
» [SI-LIST] Re: PCI-X 1.0a simulation -
» [SI-LIST] Re: PCI-X 1.0a simulation -
» [SI-LIST] Re: Test PCB structures -
» [SI-LIST] Re: Test PCB structures -
» [SI-LIST] Test PCB structures -