[SI-LIST] Re: Overshoot / Undershoot

Dear Ken
there is a nice way to give an explanation of the concern of the EMC guys:

It is enough to think about the spectrum of a signal with and without 
overshoot /undershoot.

The bandwith of the signal inthe second case is much bigger and it will 
contain significant harmonic in higher frequency
range.
 this spectral component will easily comprise the behaviour of the net : 
it will radiate much kmore efficiently !!!

Time ago I compared, by using field solver, the level of radiated field 
form a net in both cases and it is easy to show that less overshoot you 
have less field will be radiated.

 An immediate application of this concept is that sometime is a good 
idea to use termination to improve quality of the signal even in the 
case this is not necessary from functional point of view , just to 
reduce level of EMC noise

Regards
Giancarlo

Ken Willis ha scritto:
> Hi,
>
> I had a slightly different question related to this. Some 3.3V devices
> are 5V-tolerant, and per their specs can tolerate quite a bit of
> overshoot. Let's assume for a minute that the overshoot you will see
> is within the device's spec, and is such that the timing will still be
> OK. So everything should be functional and within spec for SI/timing
> purposes.
>
> Some of the EMI folks I have worked with in hardware development have
> expressed concern about leaving a bus like this with excessive (ex. 2v)
> overshoot, even if it is within the device specs. The thinking here is
> that every time the bus switches, it can have 64 (or however many) bits
> with overshoot at their receivers, turning on their associated clamp
> diodes,
> and shooting nice spikes of current into the power/ground system. Some
> view
> this as a bunch of little noise sources, exciting the planes, and
> potentially
> lighting heatsinks, cables, other critical components, etc. nearby.
>
> So for EM compliance reasons and general robustness of the system, it
> seems
> like it may be desireable to terminate buses of this nature, even if it
> is
> OK by traditional SI/timing points of view. I was curious to see if
> folks
> are generally content to let buses like this thump away with the
> overshoot,
> or if they usually strive to terminate them in their typical
> methodologies.
>
> Ken
>
>
> -----Original Message-----
> From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
> On Behalf Of Bill.Cohen@xxxxxxxxxxxxxxxx
> Sent: Thursday, January 12, 2006 7:45 PM
> To: andrew.seddon@xxxxxxxxxxxx
> Cc: si-list@xxxxxxxxxxxxx
> Subject: [SI-LIST] Re: Overshoot / Undershoot
>
> Andrew,
>
> JEDEC has an overshoot/undershoot specification for DDR2 a 1.8V
> technology.
> Older technologies relied on an absolute voltage but the newer
> technologies work on an absolute maximum and an area (above/below power)
> of stress. This area limits the overshoot stress into a maximum stress
> for a period of time. The long time reliability of the gate oxide is at
> issue here and the duty cycle of the signal also comes into play. Look
> at the DDR2 datasheet
> (JEDEC.org) and look at the stress model they have for
> undershoot/overshoot of input signals. We have incorporated this model
> into our latest specifications.
>
> Best Regards,
>
> --------------------------------------------------------------
> | Bill Cohen
> | Toshiba America Electronic Components
> | Mixed Signal Design Group
> --------------------------------------------------------------
>
>
> =20
>
>              "Andrew Seddon"
>
>              <andrew.seddon@ca
>
>              msig.co.uk>
> To=20
>              Sent by:                  <si-list@xxxxxxxxxxxxx>
>
>              si-list-bounce@fr
> cc=20
>              eelists.org
>
> =20
> Subject=20
>                                        [SI-LIST] Overshoot / Undershoot
>
>              01/12/2006 07:30
>
>              PM
>
> =20
>
> =20
>
>              Please respond to
>
>              andrew.seddon@cam
>
>                  sig.co.uk
>
> =20
>
> =20
>
>
>
>
>
> Hello,
>
>
> I was wondering if anybody had an idea of what is a typically acceptable
> bad but workable overshoot/undershoot on a 3.3V system? For example I
> see some memory IC's can take transients upto 5.5v where as the
> datasheet max is say
> +0.3. Obviously this figure is based on DC.
>
> I presume the major effect's of over/under shoot are to reduce working
> life of the IC and make the circuit potentially fail at temperature
> extremes?
>
> So when you guys analyse overshoot/undershoot how do you decide if it's
> acceptable?
>
> Kind regards,
>
> Andrew
>
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