[SI-LIST] Re: Overshoot / Undershoot
- From: "Andrew Seddon" <andrew.seddon@xxxxxxxxxxxx>
- To: <si-list@xxxxxxxxxxxxx>
- Date: Tue, 13 Sep 2005 17:24:57 +0100
The 5.5v spec I mentioned was a pretty extreme case.
However say due to net topology restrictions I can only get the
overshoot/undershoot down to 1v on a 3.3V part, lasting for 500ps. Would
this be too much for most common memory's/processor's/peripherals?
Thanks,
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On
Behalf Of Tom Dagostino
Sent: 13 January 2006 17:17
To: kwillis@xxxxxxxxxxx; si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: Overshoot / Undershoot
Ken
I have never seen a 5V tolerant 3.3V device that had a clamp device tied to
3.3V. I have seen a few 5V tolerant parts that had clamps that turned on
past 5.5V. 99.999% of the devices we have measured have ground clamps. If
you have overshoot (defined as a short duration spike above the normal high
or low level of the driver) of 2 Volts in the rising direction you will
likely also have it on the falling edge. You will need to control it in
both directions.
Tom Dagostino
Teraspeed(R) Labs
13610 SW Harness Lane
Beaverton, OR 97008
503-430-1065
tom@xxxxxxxxxxxxx
www.teraspeed.com
Teraspeed Consulting Group LLC
121 North River Drive
Narragansett, RI 02882
401-284-1827
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx
[mailto:si-list-bounce@xxxxxxxxxxxxx]On Behalf Of Ken Willis
Sent: Friday, January 13, 2006 6:25 AM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: Overshoot / Undershoot
Hi,
I had a slightly different question related to this. Some 3.3V devices
are 5V-tolerant, and per their specs can tolerate quite a bit of
overshoot. Let's assume for a minute that the overshoot you will see
is within the device's spec, and is such that the timing will still be
OK. So everything should be functional and within spec for SI/timing
purposes.
Some of the EMI folks I have worked with in hardware development have
expressed concern about leaving a bus like this with excessive (ex. 2v)
overshoot, even if it is within the device specs. The thinking here is
that every time the bus switches, it can have 64 (or however many) bits
with overshoot at their receivers, turning on their associated clamp
diodes,
and shooting nice spikes of current into the power/ground system. Some
view
this as a bunch of little noise sources, exciting the planes, and
potentially
lighting heatsinks, cables, other critical components, etc. nearby.
So for EM compliance reasons and general robustness of the system, it
seems
like it may be desireable to terminate buses of this nature, even if it
is
OK by traditional SI/timing points of view. I was curious to see if
folks
are generally content to let buses like this thump away with the
overshoot,
or if they usually strive to terminate them in their typical
methodologies.
Ken
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
On Behalf Of Bill.Cohen@xxxxxxxxxxxxxxxx
Sent: Thursday, January 12, 2006 7:45 PM
To: andrew.seddon@xxxxxxxxxxxx
Cc: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: Overshoot / Undershoot
Andrew,
JEDEC has an overshoot/undershoot specification for DDR2 a 1.8V
technology.
Older technologies relied on an absolute voltage but the newer
technologies work on an absolute maximum and an area (above/below power)
of stress. This area limits the overshoot stress into a maximum stress
for a period of time. The long time reliability of the gate oxide is at
issue here and the duty cycle of the signal also comes into play. Look
at the DDR2 datasheet
(JEDEC.org) and look at the stress model they have for
undershoot/overshoot of input signals. We have incorporated this model
into our latest specifications.
Best Regards,
--------------------------------------------------------------
| Bill Cohen
| Toshiba America Electronic Components
| Mixed Signal Design Group
--------------------------------------------------------------
=20
"Andrew Seddon"
<andrew.seddon@ca
msig.co.uk>
To=20
Sent by: <si-list@xxxxxxxxxxxxx>
si-list-bounce@fr
cc=20
eelists.org
=20
Subject=20
[SI-LIST] Overshoot / Undershoot
01/12/2006 07:30
PM
=20
=20
Please respond to
andrew.seddon@cam
sig.co.uk
=20
=20
Hello,
I was wondering if anybody had an idea of what is a typically acceptable
bad but workable overshoot/undershoot on a 3.3V system? For example I
see some memory IC's can take transients upto 5.5v where as the
datasheet max is say
+0.3. Obviously this figure is based on DC.
I presume the major effect's of over/under shoot are to reduce working
life of the IC and make the circuit potentially fail at temperature
extremes?
So when you guys analyse overshoot/undershoot how do you decide if it's
acceptable?
Kind regards,
Andrew
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