What techniques are people using to combine the results of static timing and signal integrity analysis for closing timing at the board/system level? This is a question I've asked a few times before, usually with mixed responses. Because the choices for board-level static timing tools are relatively few, I'm curious as to which tools are used productively, and how. Replies on and off the list are welcome. Thanks, Todd. Todd Westerhoff High Speed Design Specialist Cisco Systems 1414 Massachusetts Ave - Boxboro, MA - 01719 email:twesterh@xxxxxxxxx ph: 978-936-2149 ============================================ "Always do right. This will gratify some people and astonish the rest." - Mark Twain ------------------------------------------------------------------ To unsubscribe from si-list: si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field or to administer your membership from a web page, go to: //www.freelists.org/webpage/si-list For help: si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field List FAQ wiki page is located at: http://si-list.org/wiki/wiki.pl?Si-List_FAQ List technical documents are available at: http://www.si-list.org List archives are viewable at: //www.freelists.org/archives/si-list or at our remote archives: http://groups.yahoo.com/group/si-list/messages Old (prior to June 6, 2001) list archives are viewable at: http://www.qsl.net/wb6tpu