[SI-LIST] Re: On a different note ....
- From: Bill Wurst <billw@xxxxxxxxxxx>
- To: si-list@xxxxxxxxxxxxx
- Date: Fri, 24 Sep 2004 11:32:31 -0400
As clock rates increase and timing margins shrink, it seems to me that
crosstalk induced timing modulation is becoming more of an issue, both on
ASICs and PCBs. This and the complexity of todays designs will probably
force us to move away from Excel spreadsheets which I, like many others,
haveused for timing analysis. What I mean by crosstalk induced timing
modulation is this: Envision a victim net with with one or more aggressors.
At roughly this same time that the victim transitions, the aggressor(s)
transition also. Depending on whether the aggressors move in the same or
opposite directions, the timing on the victim will either be advanced or
retarded. Admittedly, this variation is small (on the order of the
transition time of the signals involved), but timing margins today are often
of the same order or less.
It would seem that tools like Mentor's ICX / Tau combination are ideally
suited to analyze this situation on PCBs (IBM's static timing tool,
Einstimer, has had this capability for a couple of years now for ASICs).
Does anyone know if this capability exists in Mentor's tools yet (Mentor's
salesmen told me this was coming a year ago) and if so, does it work? Does
anyone have any experience with these tools to give some feedback.
Another tool that was supposed to be enhanced for this capability is
SiAuditor [1]from SiSoft[2]. Does anyone have any experience with this tool
to report - good, bad, or otherwise?
Thanks,
-Bill
======================
Peterson, James F (FL51) wrote:
yep - I agree with you in general, regarding home-grown tools. The excel
approach to board level timing is simple and elegant - we dedicate a page to
device timing, a page to trace timing, and then a page to each interface
analyzed. We've found that it's easy to understand (you can past in timing
diagrams, show the equations, and add notes to help understand each of the
interfaces) and it's nice to have everything in one model. We've been using
it for around 4 years now and there are so many positives that the EDA
vendortool that wants to compete will have a tough sell. But that said,
thereare some out there that have some potential - I believe Mentor's TAU is
one of them. I mentioned there are some weaknesses to our approach. It's
cumbersome for us to break down a bus to the individual signal level : when
we give a min/max it's at the bus level. the challenge is, say on a hold
timeissue, that the signal whose trace has the quickest settling time on the
bus, doesn't have the quickest Tco(min) at the chip, so we're overly
conservative. It's cumbersome for our approach to break this down, we can do
it but it becomes complicated, and harder to understand and maintain. This
iswhere the EDA tools that I've seen are more efficient. best regards, Jim
-----Original Message----- From: steve weir [mailto:weirsp@xxxxxxxxxx[3]]
Sent: Friday, September 24, 2004 7:51 AM To: james.f.peterson@xxxxxxxxxxxxx[4]
Cc: si-list@xxxxxxxxxxxxx[5] Subject: Re: [SI-LIST] Re: On a different note
.... Jim, one of the values that a vendor tool brings is that it doesn't
loaddown the organization with the task of maintaining and training people
oncustom in-house tools. In larger organizations, vendor tools even if
priceymay pay back easily in terms of the scarce engineering resources that
they save from non-core tasks. OTOH, some amount of in-house tools can
provide an edge in cost or productivity, so mileage will definitely vary.
Regards, Steve. At 04:23 AM 9/24/2004 -0700, Peterson, James F (FL51) wrote:
Todd, without going into too much detail, an excel spreadsheet can be
awesomefor developing (allocating and budgeting timing) and maintaining
(back-annotating with actual timing) a board-level timing model (see my
earlier reply in archives). there are some weaknesses in this approach that
an EDA vendor can fix by creating/selling a custom tool, but I'm currently
developing one for a board that has DDR SDRAM, QDR SRAM, and RapidIO with
LVDS, SSTL and HSTL data rates at 250MHz, and it still works. best regards,
Jim Peterson Honeywell -----Original Message----- From:
si-list-bounce@xxxxxxxxxxxxx[6] [mailto:si-list-bounce@xxxxxxxxxxxxx[7]]On
Behalf Of Todd Westerhoff (twesterh) Sent: Thursday, September 23, 2004 4:17
PM To: si-list@xxxxxxxxxxxxx[8] Subject: [SI-LIST] On a different note ....
What techniques are people using to combine the results of static timing and
signal integrity analysis for closing timing at the board/system level? This
is a question I've asked a few times before, usually with mixed responses.
Because the choices for board-level static timing tools are relatively few,
I'm curious as to which tools are used productively, and how. Replies on and
off the list are welcome. Thanks, Todd. Todd Westerhoff High Speed Design
Specialist Cisco Systems 1414 Massachusetts Ave - Boxboro, MA - 01719
email:twesterh@xxxxxxxxx[9] ph: 978-936-2149
============================================ "Always do right. This will
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-Bill
William C. Wurst William C. Wurst 2 5 2004-09-03T11:07:00Z
2004-09-03T11:07:00Z 1 30 176 Advanced Electronic Concepts, LLC 1 1 205
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-Bill
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