[SI-LIST] Re: On a different note ....
- From: "Peterson, James F (FL51)" <james.f.peterson@xxxxxxxxxxxxx>
- To: si-list@xxxxxxxxxxxxx
- Date: Fri, 24 Sep 2004 04:23:21 -0700
Todd,
without going into too much detail, an excel spreadsheet can be awesome for
developing (allocating and budgeting timing) and maintaining
(back-annotating with actual timing) a board-level timing model (see my
earlier reply in archives). there are some weaknesses in this approach that
an EDA vendor can fix by creating/selling a custom tool, but I'm currently
developing one for a board that has DDR SDRAM, QDR SRAM, and RapidIO with
LVDS, SSTL and HSTL data rates at 250MHz, and it still works.
best regards,
Jim Peterson
Honeywell
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx
[mailto:si-list-bounce@xxxxxxxxxxxxx]On Behalf Of Todd Westerhoff
(twesterh)
Sent: Thursday, September 23, 2004 4:17 PM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] On a different note ....
What techniques are people using to combine the results of static timing and
signal integrity analysis for closing timing at the board/system level?
This is a question I've asked a few times before, usually with mixed
responses. Because the choices for board-level static timing tools are
relatively few, I'm curious as to which tools are used productively, and
how.
Replies on and off the list are welcome.
Thanks,
Todd.
Todd Westerhoff
High Speed Design Specialist
Cisco Systems
1414 Massachusetts Ave - Boxboro, MA - 01719
email:twesterh@xxxxxxxxx
ph: 978-936-2149
============================================
"Always do right.
This will gratify some people and astonish the rest."
- Mark Twain
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