[SI-LIST] Re: On a different note ....
- From: Dan Bostan <dbostan@xxxxxxxxx>
- To: james.f.peterson@xxxxxxxxxxxxx, billw@xxxxxxxxxxx, si-list@xxxxxxxxxxxxx
- Date: Sat, 25 Sep 2004 08:30:21 -0700 (PDT)
We also took the Excel approach when designing a very
complex telco system.
As for the SI tool, Hyperlynx may be a good choice
(not as good as ICX or Spectraquest), as noted by
Scott earlier.
But relying on a spreadsheet, not Tau, for example,
does not provide the best tool integration, which is
reflected in development time, and potential technical
issues.
/dan
--- "Peterson, James F (FL51)"
<james.f.peterson@xxxxxxxxxxxxx> wrote:
> I probably should clear something up on our excel
> spreadsheet approach :
> the pcb trace delays in our excel spreadsheet are
> quantified by ICX, so this
> approach stands up to a lot high speed issues
> (xtalk, settling time, etc.).
> The only thing the excel spreadsheet is doing is
> keeping track of everything
> (it budgets trace delays before pcb design, and it
> tallies the real delay
> (via ICX) after pcb design).
>
> Also, keep in mind we're talking board level timing
> (original question), so
> it includes trace delays, chip delays, clk skews,
> etc. for all interfaces.
> Using ICX (or a similar tool) just gives you one
> component - a very
> important component - but we still need everything
> else.
>
> Jp
>
> -----Original Message-----
> From: si-list-bounce@xxxxxxxxxxxxx
> [mailto:si-list-bounce@xxxxxxxxxxxxx]On Behalf Of
> Bill Wurst
> Sent: Friday, September 24, 2004 11:33 AM
> To: si-list@xxxxxxxxxxxxx
> Subject: [SI-LIST] Re: On a different note ....
>
>
>
> As clock rates increase and timing margins shrink,
> it seems to me that
> crosstalk induced timing modulation is becoming more
> of an issue, both on
> ASICs and PCBs. This and the complexity of todays
> designs will probably
> force us to move away from Excel spreadsheets which
> I, like many others,
> haveused for timing analysis. What I mean by
> crosstalk induced timing
> modulation is this: Envision a victim net with with
> one or more aggressors.
>
> At roughly this same time that the victim
> transitions, the aggressor(s)
> transition also. Depending on whether the
> aggressors move in the same or
> opposite directions, the timing on the victim will
> either be advanced or
> retarded. Admittedly, this variation is small (on
> the order of the
> transition time of the signals involved), but timing
> margins today are often
> of the same order or less.
>
> It would seem that tools like Mentor's ICX / Tau
> combination are ideally
> suited to analyze this situation on PCBs (IBM's
> static timing tool,
> Einstimer, has had this capability for a couple of
> years now for ASICs).
> Does anyone know if this capability exists in
> Mentor's tools yet (Mentor's
> salesmen told me this was coming a year ago) and if
> so, does it work? Does
> anyone have any experience with these tools to give
> some feedback.
>
> Another tool that was supposed to be enhanced for
> this capability is
> SiAuditor [1]from SiSoft[2]. Does anyone have any
> experience with this tool
> to report - good, bad, or otherwise?
>
> Thanks,
> -Bill
> ======================
> Peterson, James F (FL51) wrote:
> yep - I agree with you in general, regarding
> home-grown tools. The excel
> approach to board level timing is simple and elegant
> - we dedicate a page to
> device timing, a page to trace timing, and then a
> page to each interface
> analyzed. We've found that it's easy to understand
> (you can past in timing
> diagrams, show the equations, and add notes to help
> understand each of the
> interfaces) and it's nice to have everything in one
> model. We've been using
> it for around 4 years now and there are so many
> positives that the EDA
> vendortool that wants to compete will have a tough
> sell. But that said,
> thereare some out there that have some potential - I
> believe Mentor's TAU is
> one of them. I mentioned there are some weaknesses
> to our approach. It's
> cumbersome for us to break down a bus to the
> individual signal level : when
> we give a min/max it's at the bus level. the
> challenge is, say on a hold
> timeissue, that the signal whose trace has the
> quickest settling time on the
> bus, doesn't have the quickest Tco(min) at the chip,
> so we're overly
> conservative. It's cumbersome for our approach to
> break this down, we can do
> it but it becomes complicated, and harder to
> understand and maintain. This
> iswhere the EDA tools that I've seen are more
> efficient. best regards, Jim
> -----Original Message----- From: steve weir
> [mailto:weirsp@xxxxxxxxxx[3]]
> Sent: Friday, September 24, 2004 7:51 AM To:
> james.f.peterson@xxxxxxxxxxxxx[4]
> Cc: si-list@xxxxxxxxxxxxx[5] Subject: Re: [SI-LIST]
> Re: On a different note
> .... Jim, one of the values that a vendor tool
> brings is that it doesn't
> loaddown the organization with the task of
> maintaining and training people
> oncustom in-house tools. In larger organizations,
> vendor tools even if
> priceymay pay back easily in terms of the scarce
> engineering resources that
> they save from non-core tasks. OTOH, some amount of
> in-house tools can
> provide an edge in cost or productivity, so mileage
> will definitely vary.
> Regards, Steve. At 04:23 AM 9/24/2004 -0700,
> Peterson, James F (FL51) wrote:
> Todd, without going into too much detail, an excel
> spreadsheet can be
> awesomefor developing (allocating and budgeting
> timing) and maintaining
> (back-annotating with actual timing) a board-level
> timing model (see my
> earlier reply in archives). there are some
> weaknesses in this approach that
> an EDA vendor can fix by creating/selling a custom
> tool, but I'm currently
> developing one for a board that has DDR SDRAM, QDR
> SRAM, and RapidIO with
> LVDS, SSTL and HSTL data rates at 250MHz, and it
> still works. best regards,
> Jim Peterson Honeywell -----Original Message-----
> From:
> si-list-bounce@xxxxxxxxxxxxx[6]
> [mailto:si-list-bounce@xxxxxxxxxxxxx[7]]On
> Behalf Of Todd Westerhoff (twesterh) Sent: Thursday,
> September 23, 2004 4:17
> PM To: si-list@xxxxxxxxxxxxx[8] Subject: [SI-LIST]
> On a different note ....
> What techniques are people using to combine the
> results of static timing and
> signal integrity analysis for closing timing at the
> board/system level? This
> is a question I've asked a few times before, usually
> with mixed responses.
> Because the choices for board-level static timing
> tools are relatively few,
> I'm curious as to which tools are used productively,
> and how. Replies on and
> off the list are welcome. Thanks, Todd. Todd
> Westerhoff High Speed Design
> Specialist Cisco Systems 1414 Massachusetts Ave -
> Boxboro, MA - 01719
> email:twesterh@xxxxxxxxx[9] ph: 978-936-2149
> ============================================ "Always
> do right. This will
> gratify some people and astonish the rest." - Mark
> Twain
>
------------------------------------------------------------------
> To
> unsubscribe from si-list:
> si-list-request@xxxxxxxxxxxxx[10] with
> 'unsubscribe' in the Subject field or to administer
> your membership from a
> web page, go to:
> //www.freelists.org/webpage/si-list[11] For
> help:
> si-list-request@xxxxxxxxxxxxx[12] with 'help' in the
> Subject field List FAQ
> wiki page is located at:
> http://si-list.org/wiki/wiki.pl?Si-List_FAQ[13]
> Listtechnical documents are available at:
> http://www.si-list.org[14] List
> archives are viewable at:
> //www.freelists.org/archives/si-list[15] or
> atour remote archives:
> http://groups.yahoo.com/group/si-list/messages[16]
> Old(prior to June 6, 2001) list archives are
> viewable at:
> http://www.qsl.net/wb6tpu[17]
>
------------------------------------------------------------------
> To
> unsubscribe from si-list:
> si-list-request@xxxxxxxxxxxxx[18]
=== message truncated ===
_______________________________
Do you Yahoo!?
Declare Yourself - Register online to vote today!
http://vote.yahoo.com
------------------------------------------------------------------
To unsubscribe from si-list:
si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field
or to administer your membership from a web page, go to:
//www.freelists.org/webpage/si-list
For help:
si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field
List FAQ wiki page is located at:
http://si-list.org/wiki/wiki.pl?Si-List_FAQ
List technical documents are available at:
http://www.si-list.org
List archives are viewable at:
//www.freelists.org/archives/si-list
or at our remote archives:
http://groups.yahoo.com/group/si-list/messages
Old (prior to June 6, 2001) list archives are viewable at:
http://www.qsl.net/wb6tpu
Other related posts:
