[SI-LIST] On a different note ....
- From: "Todd Westerhoff (twesterh)" <twesterh@xxxxxxxxx>
- To: <si-list@xxxxxxxxxxxxx>
- Date: Thu, 23 Sep 2004 16:16:58 -0400
What techniques are people using to combine the results of static timing and
signal integrity analysis for closing timing at the board/system level?
This is a question I've asked a few times before, usually with mixed
responses. Because the choices for board-level static timing tools are
relatively few, I'm curious as to which tools are used productively, and
how.
Replies on and off the list are welcome.
Thanks,
Todd.
Todd Westerhoff
High Speed Design Specialist
Cisco Systems
1414 Massachusetts Ave - Boxboro, MA - 01719
email:twesterh@xxxxxxxxx
ph: 978-936-2149
============================================
"Always do right.
This will gratify some people and astonish the rest."
- Mark Twain
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