[SI-LIST] Re: Buried Capacitance thread comments (The whole thing)
- From: Chris Cheng <chris.cheng@xxxxxxxxxxxx>
- To: si-list@xxxxxxxxxxxxx
- Date: Mon, 3 Dec 2001 14:25:12 -0800
Mike,
Indeed it is bygones and I will promise technical discussions only.
In fact, we are getting closer to agreement in your message below.
I do not know anything about the K6 package problems and I have to
take your word about the mode conversion phenomenon is the root
cause and typically that is what I observed in some other systems
design also. Sometimes it is lumped into the so called SSO (ground/
power bounce) noise problem. I hope we agreed that this is an issue
related to I/O switching current return path. As such it is super
critical to manage the signal return path all the way from die,
package and on the PCB board itself. Whenever the return path
is broken, noise/EMI problem arises. Maybe in the heat of the
discussion, you have missed my second statement about managing
signal return paths is the key to keeping high frequency decoupling
needed on PCB. In the ideal world we would like to sandwich the
signals between the power/ground from the beginning of the signal
to the end at the other end. In a non ideal world, other methods
have to be used. In my opinion (and here is where I think the
agreement starts to diverge) the return path management happen
either on die through on die decoupling (actually we still agree
on this) or manage the signal reference planes. Here lies the
problem with 2 mil power/ground planes, they cannot be used for
the signal reference planes since the impedance control of the
signals dictated the thickness of the dielectric. In order to
used this 2 mil core dielectric, your signal traces have to be
super thin, something the current PCB technology is not possible
to achieve. Like I said in previous messages, if microstrip signal
traces on the package or on the PCB happens to be referencing to
the wrong power planes (a very very common mistake designers
made, in particular on low cost low layer count PCB), you will
see the resonance/EMI/SSO noise you mentioned. You can fixed it
by putting in lots of low esl/esr decoupling caps or you can
use your 2 mil planes to provide the low impedance path. But
the problem can also be eliminated simply by bring the signal
to at least one proper reference plane (typically ground plane)
and provide an even lower impedance return path than 2mil planes
or lots of decoupling caps.
Regards,
Chris
-----Original Message-----
From: MikonCons@xxxxxxx [mailto:MikonCons@xxxxxxx]
Sent: Monday, December 03, 2001 1:17 PM
To: ldsmith@xxxxxxxxxxxxxxxxxx; si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: Buried Capacitance thread comments (The whole
thing)
Sorry about the mud, guys. Now "bygones."
Re: Larry's comments on high frequency energy making it to the board and
causing EMI problems, this is and has been a major issue with all higher
frequency processors. The 200 MHz limit that (to quote Larry) "some one"
specified is constantly violated by processors. The original
(pre-production)
AMD K6 processor packages (prototyped by IBM, certainly a competent
manufacturer) exhibited a package resonance at 750 MHz that (per the mode
conversion phenomenon aptly noted by Scott McMorrow) leaked (or actually ran
rampant) onto the PCB and was very nicely characterized by EMI radiated
emission tests.
This problem was measured, characterized, modeled, and correctly simulated
for an indepth understanding. Multiple in-package filter alterations were
modeled and evaluated that offered attenuation exceeding 60 dB. But power
carrying ability of the resulting structure posed lower practical limits to
lower levels (as noted by Larry). And, as most of us know, on-die decoupling
capacitance goes a long way to reducing the resonant frequency and
containing
the higher frequency currents on the chip.
My (years ago) analyses of this problem clearly demonstrated the need (and
the potential) for innovative package design that is still an ongoing issue
for all processor manufacturers. Grounded heatsinks on these chips have
provided a field interseptor and shielding improvement for some of the
energy, but thin dielectric planar decoupling is a critical element on the
PCB to resolving EMI problems beyond the control of the processor package
designer.
Mike
Michael L. Conn
Owner/Principal Consultant
Mikon Consulting
Cell: (408)821-9843
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