[SI-LIST] Re: Buried Capacitance thread comments (The whole thing)

Chris and all,

Chris has provided some additional excellent clarifications which
I am generally in agreement with.  The point that he (we) make
is that if you engineer your return paths from die to die, the amount
of noise which you have to contain through decoupling, thin
dielectrics and extraordinary EMI control techniques is reduced
drastically.

It is mode conversion that is the culprit.  By controlling this at all
possible points in a design, you can eliminate the need for other
extraordinary methods of noise control.


regards,

scott


>

--
Scott McMorrow
Principal Engineer
SiQual, Signal Quality Engineering
18735 SW Boones Ferry Road
Tualatin, OR  97062-3090
(503) 885-1231
http://www.siqual.com




Chris Cheng wrote:

> Scott old pal, this is neither a fight, non am I Irish.
> You make some good reference on the imperfect nature of image
> current return. Lets take a closer look.
>
> As performance increases, people use different techniques to
> address this issue. In the not so distant past, open drain (like GTL) or
> emitter follower (like PECL or ECL) I/Os are used and they are by
> design asymmetric I/O that only need a single reference plane for
> current return to the driver (the other direction is being taken
> cared by the decoupling at the terminator) In the case of GTL, all
> the return path needs to reference is ground (Bill Gunning used
> to joke with me saying "don't call this Gunning transceiver logic, call
> it ground transceiver logic).  Similar argument for PECL or ECL
> I/O's.
> In lots of new high speed designs differential signals are use in
> which they reference to themselves (in differential mode) and
> asymmetrical reference to the terminating voltage (common mode).
>
> >From the above, asymmetric I/O is more popular than you think,
> but we still have to address the push pull drivers. It turns out in
> order to sustain the sharp edge rate even to come out of the
> package, a lot of those I/O uses on die decoupling to support
> the initial di/dt. As such they can (while "not desire" as you
> like to say) take return current asymmetrically, either from the
> ground or the i/o power through the on die decoupling.
> Most likely they will take the ground path for the return.
> As you mentioned, a lot of packages have to use microstrip
> to route the signals out. However, the so call mode conversion
> will happen at the die level through the on die decoupling such
> that once it comes out of the die, only ground reference is
> need for both transition image current to return. In that
> situation, either case 1) or 3) in your description will
> be just fine for the I/O. You can even project to case 2)
> is ok provided the power plane is the I/O power and the
> package reference planes is either power or sandwich
> between power and ground.
>
> What you didn't mention is what I consider case 2b)
> where the reference power plane is not even the I/O
> power e.g. the other power plane at a different level.
> In this situation, your mode conversion or image
> current return is broken. This is where people see
> EMI noise or signal power/ground bounce. This is
> when people bring in those EMI or SI consultants
> where they start to sprinkle in those 100's of
> pf decoupling caps or Zycon planes to provide
> the low impedance path for the image current to
> return. In my opinion, two wrongs doesn't equal
> to one right. The problem should be solved by properly
> referencing the signal return power/ground planes.
>

>
> There is another case 1b) which the power plane
> in the power/ground stripline is not the I/O power
> but other power. In this case the image current
> in the power plane has to return through the plane
> capacitance between the power/ground planes.
> Unfortunately, the spacing of the planes are
> dictated by the impedance control of the striplines
> and thin dielectric is just out of the question.
>
> Finally, since you know me a little bit, you
> should know that I used to have the luxury of 6
> well trained engineers doing power analysis
> for me on package resonance. All the plane
> resonance, via location, decoupling, plane
> discontinuity analysis are BTDT. And guess
> what, the package resonance hardly goes
> above 100MHz and you better believe I
> have the best possible package design
> available. Any other references you came
> across are in the range of 10-40MHz.
> I have mentioned this fact many, many
> times in this group and those who have
> done the same analysis have to agree with
> me. Am I trying to say PCB plane don't
> resonance? Absolutely not. Does resonance
> matter above 100MHz ? Probably not.



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