Posts for si-list, 12-2001

Browse: Last Month: 11-2001 Main Archive Page Next Month: 01-2002

» [SI-LIST] Re: Equation -
» [SI-LIST] Equation -
» [SI-LIST] Re: A question about PCI bus termination. -
» [SI-LIST] Re: SI Engineer Qualification -
» [SI-LIST] A question about PCI bus termination. -
» [SI-LIST] Re: SI Engineer Qualification -
» [SI-LIST] Re: LVPECL -to-LVDS translator -
» [SI-LIST] Re: Reflection and EMI -
» [SI-LIST] Re: SI Engineer Qualification -
» [SI-LIST] Re: SI Engineer Qualification -
» [SI-LIST] Re: SI Engineer Qualification -
» [SI-LIST] SA12E Vil and Vih -
» [SI-LIST] Re: Burried capacitor and resistor design -
» [SI-LIST] SI Engineer Qualification -
» [SI-LIST] Burried capacitor and resistor design -
» [SI-LIST] Re: PECL Tree structure -
» [SI-LIST] LVPECL -to-LVDS translator -
» [SI-LIST] LVPECL -to-LVDS translator -
» [SI-LIST] PECL Tree structure -
» [SI-LIST] Re: selection of Tx line models depending on frequency -
» [SI-LIST] 10 BASE-T RJ45 PCB Design information -
» [SI-LIST] Re: 10 BASE-T RJ45 PCB Design information -
» [SI-LIST] question LINPAR tool -
» [SI-LIST] Re: Hspice simulation for SI -
» [SI-LIST] Re: eye diagram -
» [SI-LIST] Hspice simulation for SI -
» [SI-LIST] Re: Marty Jawitz -
» [SI-LIST] Re: Hairpin? -
» [SI-LIST] Hairpin? -
» [SI-LIST] Re: eye diagram -
» [SI-LIST] eye diagram -
» [SI-LIST] selection of Tx line models depending on frequency -
» [SI-LIST] Re: selection of Tx line models depending on frequency -
» [SI-LIST] AW: Re: AW: Effects of flux on board performance -
» [SI-LIST] Reflection and EMI -
» [SI-LIST] s2ibis2 conversion -
» [SI-LIST] Re: Differential Pair -
» [SI-LIST] 100Base-T signalling -
» [SI-LIST] 10 BASE-T RJ45 PCB Design information -
» [SI-LIST] Software questions -
» [SI-LIST] Solder Mask -
» [SI-LIST] Seminars & Books - Signal Integrity Design -
» [SI-LIST] AW: Effects of flux on board performance -
» [SI-LIST] Looking for SI position in Ottawa, Canada -
» [SI-LIST] Differential Pair -
» [SI-LIST] Re: Marty Jawitz -
» [SI-LIST] Re: Cin in IBIS models -
» [SI-LIST] Re: Cin in IBIS models -
» [SI-LIST] Re: Cin in IBIS models -
» [SI-LIST] Re: Cin in IBIS models -
» [SI-LIST] Re: Cin in IBIS models -
» [SI-LIST] Re: Cin in IBIS models -
» [SI-LIST] Re: Cin in IBIS models -
» [SI-LIST] Re: Cin in IBIS models -
» [SI-LIST] Re: Cin in IBIS models -
» [SI-LIST] Re: IBIS -
» [SI-LIST] Cin in IBIS models -
» [SI-LIST] [Fwd: Resistor noise specs] -
» [SI-LIST] Resistor noise specs -
» [SI-LIST] Re: ESD protection -
» [SI-LIST] Re: ESD protection -
» [SI-LIST] Re: 2.5D -
» [SI-LIST] Re: ESD protection -
» [SI-LIST] ESD protection -
» [SI-LIST] Re: 2.5D -
» [SI-LIST] Re: PCI connector -
» [SI-LIST] OPENING: Juniper Networks: Signal Integrity Engineer -
» [SI-LIST] Re: 2.5D -
» [SI-LIST] Re: Pls let me know. -
» [SI-LIST] Pls let me know. -
» [SI-LIST] Re: PCI connector -
» [SI-LIST] Re: RMS jitter -
» [SI-LIST] Re: PCI connector -
» [SI-LIST] Re: IBIS -
» [SI-LIST] Re: IBIS -
» [SI-LIST] Re: IBIS -
» [SI-LIST] Re: IBIS -
» [SI-LIST] Re: IBIS -
» [SI-LIST] IBIS -
» [SI-LIST] Effects of flux on board performance -
» [SI-LIST] Re: RMS jitter -
» [SI-LIST] Re: RF System Design Seminars? -
» [SI-LIST] Re: RF System Design Seminars? -
» [SI-LIST] RF System Design Seminars? -
» [SI-LIST] Announcement for Photonic and Optoelectronic Packaging course at San Jose State University -
» [SI-LIST] RMS jitter -
» [SI-LIST] Re: cpu socket -
» [SI-LIST] cpu socket -
» [SI-LIST] PCI connector -
» [SI-LIST] Re: Answering Protocol -
» [SI-LIST] Re: Answering Protocol -
» [SI-LIST] Re: Question on PLL for Data/Clock Recovery Apps -
» [SI-LIST] RMS jitter -
» [SI-LIST] Re: Question on PLL for Data/Clock Recovery Apps -
» [SI-LIST] Re: Answering Protocol -
» [SI-LIST] Answering Protocol - Clarification -
» [SI-LIST] Re: Answering Protocol -
» [SI-LIST] Re: Answering Protocol -
» [SI-LIST] Answering Protocol -
» [SI-LIST] Marty Jawitz -
» [SI-LIST] Re: Question on PLL for Data/Clock Recovery Apps -
» [SI-LIST] Santa Clara Valley's EMC Society Annual Social, TONIGHT -
» [SI-LIST] Re: Question on PLL for Data/Clock Recovery Apps -
» [SI-LIST] Point to multi-point termination -
» [SI-LIST] Point to multi-point termination -
» [SI-LIST] Re: DDR SDRAM -
» [SI-LIST] Re: Buried Capacitance thread comments (The whole t hing) -
» [SI-LIST] Re: transmission line model -
» [SI-LIST] Re: 2.5D -
» [SI-LIST] Re: Buried Capacitance thread comments (The whole t hing) -
» [SI-LIST] Difficulties in opeining Embedded Decoupling pdf?? -
» [SI-LIST] Re: EMC Society contribution to SI -
» [SI-LIST] Re: Undershoot, Overshoot -
» [SI-LIST] Re: Undershoot, Overshoot -
» [SI-LIST] Re: DDR SDRAM -
» [SI-LIST] Re: DDR SDRAM -
» [SI-LIST] Re: Buried Capacitance thread comments (The whole t hing) -
» [SI-LIST] EMC Society contribution to SI -
» [SI-LIST] Re: NCMS Report and Decoupling paper now available -
» [SI-LIST] The Elusive Glitch - Part 3 -
» [SI-LIST] NCMS Report and Decoupling paper now available -
» [SI-LIST] Re: Buried Capacitance thread comments (The whole t hing) -
» [SI-LIST] Re: Ferrite Bead Models -
» [SI-LIST] Re: PRBS Data patterns -
» [SI-LIST] Re: transmission line model -
» [SI-LIST] Re: Undershoot, Overshoot -
» [SI-LIST] Re: Undershoot, Overshoot -
» [SI-LIST] Re: PCI-X Specification! - or meaning of overshoot? -
» [SI-LIST] Undershoot, Overshoot -
» [SI-LIST] Re: PRBS Data patterns -
» [SI-LIST] Re: PCI-X Specification! -
» [SI-LIST] Re: PCI-X Specification! - or meaning of overshoot? -
» [SI-LIST] FW: SEEING IS BELIEVING! Accelerant Networks DEMO's 5Gb/s ! W -
» [SI-LIST] Re: PRBS Data patterns -
» [SI-LIST] Re: PCI-X Specification! -
» [SI-LIST] Question on PLL for Data/Clock Recovery Apps -
» [SI-LIST] Re: PCI-X Specification! -
» [SI-LIST] Re: lumped model vs distributed model -
» [SI-LIST] Re: 5 Gb/s Backplane Tranceiver Demo -
» [SI-LIST] Re: PRBS Data patterns -
» [SI-LIST] Re: PCI-X Specification! -
» [SI-LIST] Slow-wave mode article -
» [SI-LIST] 5 Gb/s Backplane Tranceiver Demo -
» [SI-LIST] Re: PRBS Data patterns -
» [SI-LIST] Re: PCI-X Specification! -
» [SI-LIST] Re: PRBS Data patterns -
» [SI-LIST] PCI-X Specification! -
» [SI-LIST] PRBS Data patterns -
» [SI-LIST] Re: Ferrite Bead Models -
» [SI-LIST] Ferrite Bead Models -
» [SI-LIST] Re: lumped model vs distributed model -
» [SI-LIST] Re: lumped model vs distributed model -
» [SI-LIST] Virus Warning - Do Not Open e-mails with a subject line of "Hi" and "gone.scr" or "gone.zip" attachments!!! -
» [SI-LIST] Re: Buried Capacitance thread comments (The whole t hing) -
» [SI-LIST] Re: Buried Capacitance thread comments (The whole t hing) -
» [SI-LIST] Re: lumped model vs distributed model -
» [SI-LIST] Re: 2.5D -
» [SI-LIST] Re: Buried Capacitance thread comments (The whole t hing) -
» [SI-LIST] HSDD: Re: AC Termination -
» [SI-LIST] Re: 2.5D -
» [SI-LIST] 2.5D -
» [SI-LIST] Re: lumped model vs distributed model -
» [SI-LIST] Re: Sanmina patent on dielectric thicknesses under 4 mi ls -
» [SI-LIST] Re: Sanmina patent on dielectric thicknesses under 4 mi ls -
» [SI-LIST] Re: Buried Capacitance thread comments (The whole t hing) -
» [SI-LIST] Re: Square wave harmonics -
» [SI-LIST] Re: Buried Capacitance thread comments (The whole thing) -
» [SI-LIST] Re: Buried Capacitance thread comments (The whole thing) -
» [SI-LIST] Re: AC Termination -
» [SI-LIST] Re: Buried Capacitance thread comments (The whole thing) -
» [SI-LIST] Re: lumped model vs distributed model -
» [SI-LIST] Re: lumped model vs distributed model -
» [SI-LIST] Re: lumped model vs distributed model -
» [SI-LIST] Re: Square wave harmonics -
» [SI-LIST] Re: lumped model vs distributed model -
» [SI-LIST] Buried Capacitance & Low Inductance Packages -
» [SI-LIST] Re: lumped model vs distributed model -
» [SI-LIST] Re: Buried Capacitance thread comments (The whole thing) -
» [SI-LIST] Re: Square wave harmonics -
» [SI-LIST] Re: lumped model vs distributed model -
» [SI-LIST] Re: Buried Capacitance thread comments (The whole t hing) -
» [SI-LIST] Re: Square wave harmonics -
» [SI-LIST] Re: Buried Capacitance thread comments (The whole thing) -
» [SI-LIST] Re: Buried Capacitance thread comments (The whole thing ) -
» [SI-LIST] Re: Buried Capacitance thread comments (The whole thing) -
» [SI-LIST] Re: Buried Capacitance thread comments (The whole thing ) -
» [SI-LIST] Re: Swing control for Gigabit chips -
» [SI-LIST] Re: lumped model vs distributed model -
» [SI-LIST] Re: AC Termination -
» [SI-LIST] Re: Swing control for Gigabit chips -
» [SI-LIST] Re: lumped model vs distributed model -
» [SI-LIST] AC Termination -
» [SI-LIST] Re: Buried Capacitance thread comments (The whole thing ) -
» [SI-LIST] Re: lumped model vs distributed model -
» [SI-LIST] Re: Buried Capacitance thread comments (The whole thing ) -
» [SI-LIST] Re: Buried Capacitance thread comments (The whole thing ) -
» [SI-LIST] Deleting emails from SI-LIST -
» [SI-LIST] Re: Buried Capacitance thread comments (The whole thing) -
» [SI-LIST] Re: Buried Capacitance thread comments (The whole thing) -