[SI-LIST] Re: Buried Capacitance thread comments (The whole thing)
- From: MikonCons@xxxxxxx
- To: si-list@xxxxxxxxxxxxx
- Date: Fri, 30 Nov 2001 13:06:59 EST
Scott presents a good summary of a portion of the questions raised on this
thread by his comment below. This guidance is probably the most important one
to SI engineers.
"Chris has provided some additional excellent clarifications which
I am generally in agreement with. The point that he (we) make
is that if you engineer your return paths from die to die, the amount
of noise which you have to contain through decoupling, thin
dielectrics and extraordinary EMI control techniques is reduced
drastically."
However, other design areas impact the overall EMC performance of a design
and must be integrated with the above. These include items noted by Chris
such as beneficial planar stitching and the impact of myriads of vias.
Additionally, there are planar splits (both power and ground), EMI
confinement of on-board switching supplies (which are now often operating at
1 MHz or above), and a number of other special considerations that each
different design seems to bring up. Most of these items have been discussed
previously in the SI List forum.
One of the most prominent solutions to these other EMC problems is the use of
excellent planar bypassing/decoupling, which has been covered in-depth by
many (especially by our distinguished colleagues at Sun Microsystems; i.e.,
Larry, Ray, and Istvan). Local and board-wide capacitor decoupling is the
mainstay for lower frequency disturbances, but is limited (by inductance from
physical construction and the length of connections to the planes) to under
200 MHz. That's where the interplanar capacitance, which inherently exhibits
minimal inductance, takes over. The thinner the dielectric between the planes
to be decoupled, the better the decoupling. This rationale was the stimulus
for my earlier comments and was meant to assure our less educated colleagues
were not misled as to the "simplicity" of achieving EMC in a design. A
complex, high-density design requires implementation of all the techniques at
our disposal.
I apologize for any interpretation that I was personally attacking Chris in
my initial comments. I was stating a heated difference of opinion on a
subject I helped pioneer in the area of high-speed digital design. I'm glad
Chris responded in depth to Scott's initial comments, as he has a lot to
offer the forum. For the record, I only accept approximately one in five
consulting requests that I perceive are the most challenging/difficult. All
requests for my consulting services are by word-of-mouth recommendations as I
do not advertise; i.e., there are no "scare tactics" in my portfolio. I have
directly designed or guided over 1000 complex PCB designs in the last 16
years of consulting for an average exceeding 20 different clients per year.
My client repeat rate is >98%. In the last two years, I have not worked on an
active board that did not have some portion of the circuit(s) operating in
excess of 1 GBPS (most above 2 GBPS), and not one of them had under 2000
vias. I critique and guide from one to five board designs per client. (How
many boards does a corporate employee see each year?) My EMC modeling,
analysis, and design techniques have achieved performance on (classified)
programs that is over 60 dB (yes 60) below FCC Class B levels. Hopefully,
this background experience constitutes enough "real world" evidence so no one
thinks I am purely academic.
Good engineering to all of you.
Mike
Michael L. Conn
Owner/Principal Consultant
Mikon Consulting
Cell: (408)821-9843
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