[PCB_FORUM] Re: Very Slow Allegro v. 16.3

Mark,

 

I have seen the Illegal Model Name error recently and from what a found it appears to be a bug in Allegro 16.3 where illegal characters are part of the signal model name, the design originated in Allegro 16.2 but it did not see it as a problem while Allegro 16.3 does.  Cadence claims that the issue was corrected on one of the Hotfixes that I haven't loaded to verify.  I tried finding the actually Solution that I found on the Cadence support site a month ago but I was unable to find it today.

 

I did correct it by removing the Models that it is reporting as having illegal model names for the database as well as the local devices.dml file then recreated and re-assoicated them to the components.  In my case there were spaces and percent sign in the model name which was causing the issue.

 

Hope this helps,

Mike Catrambone

Plexus Engineering Solutions

----- Original Message -----
From: "Mark Salberg" <msalberg@xxxxxxxxxxxx>
To: icu-pcb-forum@xxxxxxxxxxxxx
Sent: Wednesday, April 6, 2011 5:57:54 AM
Subject: [PCB_FORUM] Re: Very Slow Allegro v. 16.3

Wow,
Lots of great responses.
Let's see, this is where I am at...
All pwr and gnd rats = NO_RAT...Even though the board is 99% routed.
Made global shapes rough and disabled.
I have constraints set for Prop delay / Matched Length, Impedance, Diff pairs and Cross talk. So I have to check all of these.

I will check into Same net spacing and Performance advisor.

NOTE:
I am getting this signoise error. Even though I have checked for this device is devtype and symtype and can not find it.
1. I defined all DC Nets thru Logic>Identify DC Nets
2. I ran Analyze>SI_EMI Sim>Model Assignment...selected "Discrete" only and ran Auto Setup. This was to create xnets thru all discretes for terminations.
Then I get this error message:


Another Question: Can anyone tell me where to check the Time/length factor in Allegro / CM?
Most of my constraints are set to length, but a few things set to time and need to make sure the Time Length Factor is set.

One more side note, I am using Performance Option L. Set all constraints and passed.
Then load the same board in XL (expert) and 1/2 of my prop delays fail...out of spec. If I change to pass in XL, then they fail in Performance XL.

Sorry for all the details, but didn't want to misguide anyone.

Thanks again for all of the responses!
Mark

On 4/5/2011 4:36 PM, Daniel So wrote:

Hello We had that problem when rel 16 first came. It turns out, it depended on what constraints you had on the nets and what kind of licenses you had. Cadence was not able to re-produce it because they have all the license features in their licenses. What was happening as you do a "slide", Allegro would be trying to "analysis" the net and try and check out a different license feature we didn't have, like SpecctraQuest. Thus the hesitation everytime I routed net or modified a route. I had to give them a copy of our license so they would know what features they must have to try and duplicate the situation. We had to get an local AE out to our site to figure that one out and they were very reluctant to do so. It is especially hard now with all support in India. Doing Livemeeting with the tier 1 and tier 2 support engineers didn't help any. Also certain constraints, like the impedance property would do the same things. I don't know if you situation is the same but I would look at some of the constraints since it sounds you brd file is heavily constrained. Did you try downreving your brd file to rel 16.2 to see if the situation is the same or what new constraints are you using in rel 16.3 that is not in rel 16.2. Daniel -----Original Message----- From: icu-pcb-forum-bounce@xxxxxxxxxxxxx [mailto:icu-pcb-forum-bounce@xxxxxxxxxxxxx] On Behalf Of Mark Salberg Sent: Tuesday, April 05, 2011 11:57 AM To: Cadence User Group Subject: [PCB_FORUM] Very Slow Allegro v. 16.3 Hello, I was wondering if anyone there would have any tricks to speed up Allegro. I am editing a board with quite a few Constraints in the V.16.3 CM. Whenever I slide a trace, move a via or any mod, it hangs up for 30 sec each time. I have tried changing global shapes params from smooth to rough and even disabled. Short of turning off On-Line DRC, which I do not want to do. Many DRC's to clean up. Mark ----------------------------------------------------------- To subscribe/unsubscribe: Send a message to icu-pcb-forum-request@xxxxxxxxxxxxx
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