[PCB_FORUM] Re: Very Slow Allegro v. 16.3

1)      Tools > Setup Advisor then walk through the steps, it's like the third 
one

2)      CM > Analyze, Analysis Modes, Electrical options tab, this is where you 
set Pin Delay on/off too

3)      Someone else want to chime in here?

 

From: icu-pcb-forum-bounce@xxxxxxxxxxxxx 
[mailto:icu-pcb-forum-bounce@xxxxxxxxxxxxx] On Behalf Of Mark Salberg
Sent: Wednesday, April 06, 2011 8:56 AM
To: icu-pcb-forum@xxxxxxxxxxxxx
Subject: [PCB_FORUM] Re: Very Slow Allegro v. 16.3

 

More good stuff!
Thanks guys! 
The Z axis length checking in XL would definitely explain the different lengths.
1. Where is Setup Advisor? So I can verify / define all res packs.
2. Where do I check in XL license if Z is set to on?
3. Where do I set the Time Length Factor for "timing constraints"?

Much thanks to you all. I am still trying all of your suggestions.
Regards,
Mark

On 4/6/2011 8:17 AM, Gerry Meier wrote: 

Jean,

 

Good point on R-packs - typically we have to delete the auto model and use the 
create model to create it correctly.

Typically is does not map the pins properly like 1 8 , 2 7, 3 6, 4 5 so you 
have to audit r-pack models.

 

Gerry

 

"New Phone Number"

Gerry Meier, Sr. PCB Designer

Freedom CAD Services. Inc

Voice: (256) 715-1424 or (603) 864-1350

Email:gerry.meier@xxxxxxxxxxxxxx

Skype: rgmeier3

visit us at http://www.freedomcad.com

 P  Think Green only print as needed. 

 

From: icu-pcb-forum-bounce@xxxxxxxxxxxxx 
[mailto:icu-pcb-forum-bounce@xxxxxxxxxxxxx] On Behalf Of Jean Bratton
Sent: Wednesday, April 06, 2011 7:08 AM
To: icu-pcb-forum@xxxxxxxxxxxxx
Subject: [PCB_FORUM] Re: Very Slow Allegro v. 16.3

 

And, if you have pin delays defined for any of your pins, only expert pays 
attention to them

 

Some other ideas... 

You have a lot of checks turned on at once. Parallelism is a big consumer, and 
you can avoid doing long parallel lengths a lot just by eye. Sometimes it's 
worth turning that one off, doing all the rest of the DRC cleanup carefully, 
and then turning it back on later to pick up whatever you missed.

 

I generally don't let Allegro calculate the impedance, I set up physical rule 
sets for each different impedance, and assign nets to net classes accordingly 
(or you could assign the physical cset at the net/xnet level if you want). So I 
have a rule set for 50 ohm single ended, 70 ohm single ended, 90 ohm 
differential, 100 ohm differential, or whatever and assign the trace or 
trace/space requirements that way instead of having impedance turned on. 
Impedance has to go out and look at the stackup and calculate for every net you 
work on. I doubt you want to change directions like that on this board, but it 
might be something to think about going forward.

 

As for the Signoise error, In Setup Advisor, did you run Device Setup? It looks 
like that part is a resistor network. Be sure you have those set up correctly

 

 

 

Another that was suggested to us recently, but I have not tried it yet is to 
set NODRC_SYM_SAME_PIN on high pin-count devices. The theory is that if you 
have a ton of BGA's or similar devices, the system is constantly checking 
pin-to-pin clearances, and they're never going to change unless you do 
something to the symbol. Once you've established that the parts on the board 
are OK, the checks are useless. Of course, if you start doing something like 
placing new symbols or refreshing old ones, I think you'll want to remove those 
properties at least for a check. I'd also be tempted to remove them at the end 
of the board just to prevent issues at respin. I've not fooled with this one 
yet, but it makes sense in theory anywayJ

 

Good luck!

 

From: icu-pcb-forum-bounce@xxxxxxxxxxxxx 
[mailto:icu-pcb-forum-bounce@xxxxxxxxxxxxx] On Behalf Of TEYSSIER Jean-Charles
Sent: Wednesday, April 06, 2011 7:27 AM
To: icu-pcb-forum@xxxxxxxxxxxxx
Subject: [PCB_FORUM] Re: Very Slow Allegro v. 16.3

 

Mark,

 

About differences in DRC betexween performance and XL :

XL can checks Z delay (additonal delay caused by layer change with via) and 
performance can not.

So the calculated delay is not the same if Z delay is checked.

Example : let say bord is 2mm thick. If a signal walks from top to bottom then 
to top again (two vias), the calculated lengt in XL is 4mm greater than in 
performance.

 

Jean-Charles

________________________________

De : icu-pcb-forum-bounce@xxxxxxxxxxxxx 
[mailto:icu-pcb-forum-bounce@xxxxxxxxxxxxx] De la part de Mark Salberg
Envoyé : mercredi 6 avril 2011 12:58
À : icu-pcb-forum@xxxxxxxxxxxxx
Objet : [PCB_FORUM] Re: Very Slow Allegro v. 16.3

 

Wow, 
Lots of great responses.
Let's see, this is where I am at...
All pwr and gnd rats = NO_RAT...Even though the board is 99% routed.
Made global shapes rough and disabled.
I have constraints set for Prop delay / Matched Length, Impedance, Diff pairs 
and Cross talk. So I have to check all of these.

I will check into Same net spacing and Performance advisor. 

NOTE:
I am getting this signoise error. Even though I have checked for this device is 
devtype and symtype and can not find it.
1. I defined all DC Nets thru Logic>Identify DC Nets
2. I ran Analyze>SI_EMI Sim>Model Assignment...selected "Discrete" only and ran 
Auto Setup. This was to create xnets thru all discretes for terminations.
Then I get this error message:

 
Another Question: Can anyone tell me where to check the Time/length factor in 
Allegro / CM?
Most of my constraints are set to length, but a few things set to time and need 
to make sure the Time Length Factor is set.

One more side note, I am using Performance Option L. Set all constraints and 
passed.
Then load the same board in XL (expert) and 1/2 of my prop delays fail...out of 
spec. If I change to pass in XL, then they fail in Performance XL.

Sorry for all the details, but didn't want to misguide anyone.

Thanks again for all of the responses!
Mark

On 4/5/2011 4:36 PM, Daniel So wrote: 

Hello
 
We had that problem when rel 16 first came. It turns out, it depended on what 
constraints you had on the nets and what kind of licenses you had. Cadence was 
not able to re-produce it because they have all the license features in their 
licenses. 
 
What was happening as you do a "slide", Allegro would be trying to "analysis" 
the net and try and check out a different license feature we didn't have, like 
SpecctraQuest. Thus the hesitation everytime I routed net or modified a route. 
I had to give them a copy of our license so they would know what features they 
must have to try and duplicate the situation. We had to get an local AE out to 
our site to figure that one out and they were very reluctant to do so. It is 
especially hard now with all support in India. Doing Livemeeting with the tier 
1 and tier 2 support engineers didn't help any. 
 
Also certain constraints, like the impedance property would do the same things.
 
I don't know if you situation is the same but I would look at some of the 
constraints since it sounds you brd file is heavily constrained. Did you try 
downreving your brd file to rel 16.2 to see if the situation is the same or 
what new constraints are you using in rel 16.3 that is not in rel 16.2.
 
Daniel
 
-----Original Message-----
From: icu-pcb-forum-bounce@xxxxxxxxxxxxx 
[mailto:icu-pcb-forum-bounce@xxxxxxxxxxxxx] On Behalf Of Mark Salberg
Sent: Tuesday, April 05, 2011 11:57 AM
To: Cadence User Group
Subject: [PCB_FORUM] Very Slow Allegro v. 16.3
 
Hello,
I was wondering if anyone there would have any tricks to speed up Allegro.
I am editing a board with quite a few Constraints in the V.16.3 CM. 
Whenever I slide a trace, move a via or any mod, it hangs up for 30 sec each 
time.
I have tried changing global shapes params from smooth to rough and even 
disabled.
Short of turning off On-Line DRC, which I do not want to do.
Many DRC's to clean up.
 
 
Mark
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