[SI-LIST] Re: package SSN model accuracy requirements, now Behavioral Modeling

From: "Donald Telian" <donaldt@xxxxxxxxxxx>
To: "Syed Huq" <shuq@xxxxxxxxx>
Date: Fri, 18 Mar 2005 09:48:35 -0800
Syed,

Thanks for helping us refine terminology.

Let's be careful not to mix up concepts with tools and languages.  While
it seems you want to confine "macromodeling" to something only Cadence
tools do, I believe that if you look around you will find that

macromodeling =3D=3D behavioral modeling

...and the two are used interchangeably within industry and academia.
If you reference every one of the research papers I give links to on
slide 22 - as well as the quote from Franzon - you will note that they
all use "macromodeling" in both the titles and paper texts to describe
their work in "behavioral modeling".  They use the term "macromodeling"
to refer to various implementations spanning equation-based Hspice
models, VHDL-AMS models in ICX, SPICE models in IBM PowerSPICE, etc.
And yes, "macromodeling" can also be done in DML/Espice, Pspice,
Berkeley SPICE, Verilog-AMS, and a variety of other tools/languages.

Regarding your comments about Cadence tools, I'll acknowledge that it
takes a fair amount of skill and craftsmanship to construct effective
macromodels.  However, I've yet to find a device that can not be
behaviorally modeled in the environment.  Kumar and others have shown
considerable skill in adding things like time-controlled sources, nth
derivative processing, multi-dimensional table-based controlled sources,
and such into our tools to make this possible.  Thanks to their
contributions, users have had a number of published successes (slide 21)
and implementing your BIRD95 ideas would be a snap.  If your team is
struggling with other particular implementations, Cadence can provide
you assistance in a variety of ways and would be happy to do so.

During the years while it's simpler for IC companies to encrypt and ship
their transistor layout-derived model, and model users continue to ask
for faster behavioral solutions, I think it's important that we keep an
open mind regarding the options before us.  Working together, let's
encourage those working on the various tools and languages as new
solutions emerge and keep the comments on the positive side.  It's a
challenging problem to solve.

Donald


>-----Original Message-----
>From: Syed Huq [mailto:shuq@xxxxxxxxx]=20
>Sent: Wednesday, March 16, 2005 2:44 PM
>To: Donald Telian
>Cc: si-list@xxxxxxxxxxxxx
>Subject: Re: [SI-LIST] Re: package SSN model accuracy=20
>requirements, nowBehavioral Modeling
>
>Donald,
>
>Certainly our definitions are different. What you described is=20
>what I would call behavioral modeling. There is a difference=20
>and let me explain with an example:
>
>Let's pick your tool. SpecctraQuest uses this DML scheme(which=20
>I call macromodeling), in practical applications such as ours,=20
>we see the tool choking in many aspects in it's use of macro=20
>modeling. Hence I would like to stay far away from such an=20
>approach(macromodeling I mean). Maybe version 20.x would have=20
>it all sovled. I am sure there are 10s of other application=20
>where is excels quite well too.
>
>On the other side, behavioral modeling (atleast again in our
>applications) has already proven it's capabilities many times=20
>over and I am more than open to explore further with tools to=20
>see how BIRD95 could be implemented thru "behavioral modeling".
>
>Syed
>
>On Wed, 2005-03-16 at 10:14, Donald Telian wrote:
>> Syed,
>>=20
>> Sounds like our definitions of macromodeling are different. =20
>According=20
>> to my definition when you put a current source in parallel with a B=20
>> element and an RLC circuit to demonstrate IvsT BIRD95, you were=20
>> "macromodeling".  My proposal to the IBIS Committee is to=20
>allow/enable=20
>> clever engineers to invent solutions just as you have done. =3D20
>>=20
>> Call it what you will, but your IvsT implementation is a classic=20
>> example of what I'm talking about enabling.  Wouldn't you agree that=20
>> allowing SPICE B elements, paramters, and various current sources=20
>> would permit others to make and distribute models such as yours=20
>> *within the spec*?=3D20
>>=20
>> Donald
>>=20
>>=20
>> >-----Original Message-----
>> >From: Syed Huq [mailto:shuq@xxxxxxxxx]=3D20
>> >Sent: Monday, March 14, 2005 6:35 PM
>> >To: Donald Telian
>> >Cc: weirsi@xxxxxxxxxx; si-list@xxxxxxxxxxxxx; Michael=20
>Mirmak;=3D20 Gary=20
>> >Pratt; Chris.Cheng@xxxxxxxxxxxx
>> >Subject: Re: [SI-LIST] Re: package SSN model accuracy=3D20=20
>> >requirements, nowBehavioral Modeling
>> >
>> >Donald,
>> >
>> >A correction of your statement below:
>> >
>> >>In 1992 Arpad designed the first IBIS implementation using=20
>SPICE =3D20=20
>> >>macromodeling and still today Cisco used it to demonstrate=3D20
>> >their BIRD =3D20
>> >>95/SSN implementation at the Jan05 Summit.
>> >
>> >Cisco *did not* use macromodeling to demonstrate BIRD95/SSN=20
>as=3D20 you=20
>> >have stated. Our data showed comparison of HSPICE(xtor=3D20 level),=20
>> >IBISv3.2 and the new IvsT sims(BIRD95).
>> >
>> >- Syed
>> >Cisco Systems, Inc
>> >
>> >On Mon, 2005-03-14 at 18:01, Donald Telian wrote:
>> >> Steve,
>> >>=3D20
>> >> Thanks for puzzling over this with us.  As the author of the=3D20  =

>> >>data/proposal you mention below, I'd like to add a couple=3D20
>> >more thoughts.
>> >> http://www.eda.org/pub/ibis/summits/jan05/telian.pdf
>> >>=3D20
>> >> If you look towards the end of the presentation I point out that=20
>> >>SI=3D20  engineers have used SPICE effectively for behavioral=3D20
>> >modeling for many=3D20
>> >> years.  In 1992 Arpad designed the first IBIS implementation=20
>> >> using=3D20 SPICE macromodeling and still today Cisco used it =
to=3D20
>> >demonstrate their=3D20
>> >> BIRD 95/SSN implementation at the Jan05 Summit.  In the=20
>years in=3D20=20
>> >> between Cadence used behavioral SPICE macromodeling to implement=20
>> >> not=3D20 only IBIS 3.2/4.0 structures, but also many other=20
>complex=3D20
>> >devices (see=3D20
>> >> presentation).
>> >>=3D20
>> >> The proposal to the IBIS Committee was to enable common=3D20
>> >SPICE elements=3D20
>> >> as an additional way to do behavioral modeling.  While there is=20
>> >> a=3D20 serious chicken and egg problem with AMS, there is much =
less=20
>> >> of a=3D20 problem with behavioral SPICE.  It is more common to =
SI=3D20
>> >engineers, and=3D20
>> >> it is here today in many tools.  The problem is that IBIS 4.1=20
>> >> limits=3D20 itself to "Berkeley SPICE" which hasn't been updated=20
>> >> since=3D20
>> >1993.  Yet=3D20
>> >> a couple more elements would make even that fairly=3D20
>> >effective.  If you=3D20
>> >> think an extension like this would be a good idea, you=3D20
>> >should let the=3D20
>> >> IBIS Committee know.
>> >>=3D20
>> >> Some view the proposal to augment IBIS' definition of=20
>"SPICE" as=3D20 =20
>> >>competing with AMS.  I view it as a complementary step towards=3D20 =
=20
>> >>enabling progress with behavioral modeling.  All languages=3D20 =20
>> >>(Verilog-AMS, VHDL-AMS, SPICE) have their merits to those who=20
>> >>speak=3D20  them, and currently many are more fluent in SPICE.  The =

>> >>IBIS=3D20
>> >Committee=3D20
>> >> could offer a good service by providing model templates for=3D20
>> >structures=3D20
>> >> beyond native IBIS syntax in a variety of languages.  It's =
the=3D20=20
>> >> device's behavior/structure that must be understood and modeled;=20
>> >> the=3D20 question of the best language is secondary.  The basic=20
>> >> IBIS=3D20
>> >2.1 driver=3D20
>> >> was an important structure to model, and now there are more.
>> >>=3D20
>> >> Whatever we do with behavioral modeling, it will not=20
>likely be a=3D20 =20
>> >>complete replacement for layout-derived transistor-based=3D20
>> >SPICE models=3D20
>> >> anytime soon.  They will not go away.  As such,=20
>behavioral and=3D20 =20
>> >>transistor model types must co-exist.  And that seems an=20
>> >>additional=3D20  reason to enable SPICE-based macromodeling.
>> >>=3D20
>> >> Donald Telian
>> >>=3D20
>> >>=3D20
>> >>=3D20
>> >> >-----Original Message-----
>> >> >From: si-list-bounce@xxxxxxxxxxxxx=3D3D20=3D20
>> >> >[mailto:si-list-bounce@xxxxxxxxxxxxx] On Behalf Of steve weir
>> >> >Sent: Friday, March 11, 2005 5:56 PM
>> >> >To: Mirmak, Michael; gary_pratt@xxxxxxxxxxx;=3D3D20=3D20=20
>> >> >Chris.Cheng@xxxxxxxxxxxx; si-list@xxxxxxxxxxxxx
>> >> >Subject: [SI-LIST] Re: package SSN model accuracy requirements
>> >> >
>> >> >Michael, you are very welcome.  I just don't know any easy=3D20
>> >way=3D3D20 to=3D20
>> >> >get past this chicken and egg problem.  Widespread Si=3D3D20=20
>> >> >vendor=3D20 support tends to want to wait for OEM customer pull.=20
>> >> >=3D3D20 OEM=3D20 customers won't pull without Si vendor support, =
and=20
>> >> >tools=3D3D20=3D20 in-place.  Consequently, OEM customers hesitate =

>> >> >to=3D20
>> >purchase=3D3D20 tools=3D20
>> >> >for specific capability that doesn't get used.  And tool=3D3D20 =
=3D
>> vendors=3D20
>> >> >sure don't have a monetary incentive to give away new=3D3D20 =3D
>> capability=3D20
>> >> >for free.  It seems this places us at something of=3D3D20=20
>an impasse.
>> >> >
>> >> >Just brainstorming a little bit, what it might take is for=20
>> >> >the=3D3D20=3D20 tool vendors to essentially provide both tools =
and=20
>> >> >support=3D20
>> >to=3D3D20 the=3D20
>> >> >Si industry gratis so that the libraries get built. =20
>With=3D3D20=3D20=20
>> >> >libraries in place that can be demonstrated provide value,=3D3D20 =

>> >> >OEMs =3D
>>=20
>> >> >would be far more inclined to purchase the tools to=20
>use=3D3D20 AMS.=20
>> >> >=3D20 Maybe if the industry could convince the US DoD that=20
>AMS=3D3D20=20
>> >> >is=3D20 necessary for advanced military H/W, we could plow=20
>some=3D3D20=20
>> >> >gov't=3D20 dollars into this effort to prime the pump.  If=20
>> >> >funds=3D3D20 were=3D20 provided to Si vendors with the specific=20
>> >> >requirement=3D20
>> >that=3D3D20 silicon=3D20
>> >> >has to be delivered with AMS models that match SPICE=3D3D20=3D20
>> >accuracy, we=3D20
>> >> >might get somewhere.
>> >> >
>> >> >Regards,
>> >> >
>> >> >Steve.
>> >> >
>> >> >At 05:42 PM 3/11/2005 -0800, Mirmak, Michael wrote:
>> >> >>Steve et al,
>> >> >>
>> >> >>Thanks for your comments and for visiting the IBIS Summit=3D3D20
>> >> >presentation=3D3D20
>> >> >>site.
>> >> >>
>> >> >>While I cannot comment on specific vendors' tools, I do=20
>have a=3D20=20
>> >> >>few=3D3D20 general observations about IBIS and SPICE in=20
>the industry.
>> >> >>
>> >> >>Discussions about SPICE versus traditional IBIS versus IBIS=20
>> >> >>with=3D20 AMS=3D3D20 may be missing a larger point: as is =
apparent=20
>> >> >>from this=3D20 thread alone,=3D3D20 not everyone is convinced =
that=20
>> >> >>behavioral=3D20
>> >modeling=3D20
>> >> >>can be more=3D3D20 compelling than transistor-level=20
>modeling for=3D20=20
>> >> >>certain=3D3D20
>> >> >applications.  We=3D3D20
>> >> >>-- EDA vendors, system designers and silicon vendors,=20
>as you=3D3D20
>> >> >point out=3D3D20
>> >> >>-- need to review and demonstrate publicly that proper=3D20
>> >behavioral=3D3D20=3D20
>> >> >>modeling *per
>> >> >>se* can have significant advantages over transistor-level=3D20=20
>> >> >>solutions,=3D3D20 particularly proprietary ones.
>> >> >>
>> >> >>I personally believe that behavioral modeling can provide=20
>> >> >>the=3D3D20
>> >> >speed and=3D3D20
>> >> >>accuracy required by the industry for large system simulations.=20
>> >> >>=3D20 I=3D3D20 further believe that behavioral modeling, if=3D20
>> >approached with an=3D20
>> >> >>eye=3D3D20 toward flexibility and standardization, can ease some =

>> >> >>of=3D20 the=3D3D20 information exchange, feature support and=20
>> >> >>correlation=3D20 issues=3D3D20
>> >> >mentioned earlier.
>> >> >>
>> >> >>Will behavioral modeling specification extensions and=20
>> >> >>improvements=3D20 be=3D3D20 needed as designs advance?  =
Certainly. =20
>> >> >>However, as an=3D3D20
>> >> >example, I would=3D3D20
>> >> >>offer that BSIM is not exactly static; it has been =
updated=3D3D20
>> >> >and changed=3D3D20
>> >> >>regularly, as effects considered unimportant become=20
>more prominent.
>> >> >>Further, BSIM and proprietary SPICEs are themselves=20
>behavioral=3D20=20
>> >> >>model=3D3D20 sets for transistor devices -- behavioral=20
>modeling at=20
>> >> >>a=3D20 lower=3D3D20
>> >> >level of=3D3D20
>> >> >>abstraction, in other words.  Some semiconductor vendors=20
>> >> >>even=3D3D20
>> >> >use their=3D3D20
>> >> >>own internal transistor model equation sets for their own=3D3D20
>> >> >needs, beyond=3D3D20
>> >> >>what commercial tools or BSIM can offer.
>> >> >>
>> >> >>Is there a barrier to switching to abstract behavioral=20
>approaches?
>> >> >>Definitely.  In many cases, the barrier is as Chris pointed=20
>> >> >>out=3D20 --=3D3D20 low-level design and layout teams tend to =
use=3D20=20
>> >> >>SPICE-oriented=3D3D20
>> >> >tools, and=3D3D20
>> >> >>netlist extraction/encryption takes less effort (and=20
>know-how)=3D20=20
>> >> >>than=3D3D20 creating a correlated behavioral model.  Again, we=20
>> >> >>need=3D20 to=3D3D20
>> >> >demonstrate=3D3D20
>> >> >>that the advantages of more abstract behavioral modeling=3D20=20
>> >> >>approaches=3D3D20 justify the time needed to create and=3D20
>> >correlate those=3D20
>> >> >>models.  Once=3D3D20 that is demonstrated, the more specific=20
>> >> >>choices=3D20 regarding behavioral=3D3D20 modeling styles and=20
>> >> >>features=3D20
>> >become easier to make.
>> >> >>
>> >> >>The IBIS 4.1 specification supports the VHDL-AMS and=3D20
>> >Verilog-AMS=3D3D20=3D20
>> >> >>languages plus Berkeley SPICE.  The IBIS community is now=3D3D20
>> >> >hard at work=3D3D20
>> >> >>developing models and modeling techniques using these=20
>> >> >>languages,=3D20 plus=3D3D20 analyzing other behavioral modeling=20
>> >> >>proposals to=3D20
>> >address the=3D20
>> >> >>issues=3D3D20 above.  We are trying to "make the case" for=3D20
>> >behavioral=3D3D20
>> >> >modeling and to=3D3D20
>> >> >>offer accurate, standard solutions in the near term.  Your=20
>> >> >>input=3D20 is=3D3D20 welcome, particularly on how best we can =
make=20
>> >> >>that case =3D
>> to=3D3D20
>> >> >the industry.
>> >> >>We can use all the help we can get in this. :)
>> >> >>
>> >> >>- Michael Mirmak
>> >> >>   Intel Corp.
>> >> >>   Chair, EIA IBIS Open Forum
>> >> >>
>> >> >>   http://www.eigroup.org/ibis/
>> >> >>   http://www.eda.org/ibis/
>> >> >>
>> >> >>
>> >> >>-----Original Message-----
>> >> >>From: si-list-bounce@xxxxxxxxxxxxx=3D3D20=3D20
>> >> >>[mailto:si-list-bounce@xxxxxxxxxxxxx]
>> >> >>On Behalf Of steve weir
>> >> >>Sent: Friday, March 11, 2005 1:35 PM
>> >> >>To: gary_pratt@xxxxxxxxxxx; =
Chris.Cheng@xxxxxxxxxxxx;=3D3D20=3D20=20
>> >> >>si-list@xxxxxxxxxxxxx
>> >> >>Subject: [SI-LIST] Re: package SSN model accuracy requirements
>> >> >>
>> >> >>Gary, I was looking at the IBIS Summit information, and a=3D3D20
>> >> >couple of the=3D3D20
>> >> >>presentations make it apparent that compliance and usage=3D3D20
>> >> >beyond 2.0 is=3D3D20
>> >> >>poor.  Cadence in particular did a survey that showed that=20
>> >> >>SPICE=3D20 is=3D3D20 taking a lot of ground from IBIS because =
the=20
>> >> >>IBIS world has =3D
>>=20
>> >> >>not=3D3D20 provided the models needed for OEMs to get their=3D20
>> >jobs done. =3D20
>> >> >>I guess=3D3D20 this all sounds great if you're Synopsys.
>> >> >>
>> >> >>I think that if this situation is to reverse, it is going =
to=3D20=20
>> >> >>require=3D3D20 some real courage and $$$ from:  tool vendors,=20
>> >> >>silicon =3D
>>=20
>> >> >>vendors, and=3D3D20 OEMs to get over the hump and make IBIS=20
>> >> >>w/AMS=3D20 something that reverses=3D3D20 the trend towards =
SPICE. =20
>> >> >>How=3D20
>> >will Mentor=3D20
>> >> >>and Cadence=3D3D20
>> >> >convince Synopsys=3D3D20
>> >> >>to play when the current trend favors Synopsys?  Who is=3D20
>> >going to=3D3D20=3D20
>> >> >>champion this at the IC vendors when their customers =
almost=3D3D20
>> >> >universally=3D3D20
>> >> >>have H-SPICE capability and not a spiffy 4.1+ compliant=20
>IBIS=3D3D20
>> >> >tool with=3D3D20
>> >> >>engineers trained and willing to use it?
>> >> >>
>> >> >>Don't get me wrong, I like the reported results of AMS =
and=3D3D20
>> >> >the benefits=3D3D20
>> >> >>it brings.  I just see a major set of market hurdles.
>> >> >>
>> >> >>Regards,
>> >> >>
>> >> >>
>> >> >>Steve.
>> >> >
>> >> >The weirsp@xxxxxxxxxx e-mail address will terminate=20
>March 31, 2005.
>> >> >Please update your address book with weirsi@xxxxxxxxxx
>> >> >
>> >> >
>> >>=20
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