[SI-LIST] Re: package SSN model accuracy requirements, now Behavioral Modeling

From: "Muranyi, Arpad" <arpad.muranyi@xxxxxxxxx>
To: <si-list@xxxxxxxxxxxxx>
Date: Tue, 22 Mar 2005 15:58:25 -0800
Abbey,

Here are links to two books.  (Be careful, these are long links and
may wrap by the time you get this message).

1st link (ISBN 1-55860-749-8):

http://books.elsevier.com/us/mk/us/subindex.asp?isbn=3D1558607498&country=
=3DUnited+States&community=3Dmk&mscssid=3DMJ408TDN1W678MWBLCM7JN7GRT2HD5P=
2


2nd link (ISBN 1-4020-8044-1):

http://www.springeronline.com/sgw/cda/frontpage/0,0,4-0-22-33975588-0,0.h=
tml


In addition to these, the major simulator tool vendors offer tutorials
to their favorite languages...

Arpad
------------------------------------------------------------------------




-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] =
On Behalf Of Abdulrahman Rafiq
Sent: Tuesday, March 22, 2005 3:38 PM
Cc: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: package SSN model accuracy requirements, now =
Behavioral Modeling

Arpad,

Thanks for the distinctions you made between Spice and AMS. Could you=20
possible recomend a text, papers or websites where one could learn more=20
about AMS modeling and writing AMS equations?


Regards,


Abbey
(Abdulrahman Rafiq)


Muranyi, Arpad wrote:

>Sorry for joining this thread so late, but I was out of my office for a
>while.  I would like to add a few my thoughts for brain-food.
>
>I am happy to note that the discussion finally concluded that basically
>all models are behavioral, including the SPICE transistor or resistor
>models.  Having said that I hope we can also conclude that the problems
>we have with IBIS are not because it is behavioral.  In my opinion it =
is
>simply a poorly written specification.  The limitations are mostly =3D
>caused
>by the rigidity of the spec, and the close relationship between the
>keywords and their predefined (assumed) meaning.
>
>Most people don't think about this, but SPICE is suffering from the =
same
>exact problem.  It may be on a different level, but the problem is the =
=3D
>same.
>This was actually discussed several years ago in an IBIS Summit =3D
>presentation:
>
>http://www.eda.org/pub/ibis/summits/sep00/secasiu.zip
>
>To sum it up, think about the various "level"-s of MOSFET (or any other
>element) models.  When a semiconductor company invents a new process =
for
>which the existing models are inadequate, a new set of equations and a =
=3D
>new
>model "level" needs to be invented.  The implementation of this can =
only
>be done by the SPICE tool vendor, no one else.  The users of the SPICE =
=3D
>tool
>will have to wait, just like in the case of IBIS.  This is where the =
=3D
>*-AMS
>languages come to a rescue.
>
>Another thing that most people don't seem to consider is that the =3D
>equations
>of the SPICE primitives can be, and have already been converted to =
*-AMS =3D
>in
>several projects.  Therefore an AMS simulator can be used the same =
exact =3D
>way
>as if it was a SPICE simulator.  But why bother going to AMS if we have =
=3D
>SPICE?
>
>Well, the advantage of AMS over SPICE is that we get access to the =3D
>equations.
>We don't have to wait for the tool vendor to implement anything for us, =
=3D
>we
>can write it any time we want it to.  Also, having that access to the =
=3D
>equations,
>the model maker can decide what level of abstraction they should use =
for =3D
>their
>model.  They can choose to do it as we know it from SPICE (using =
circuit =3D
>elements,
>such as R, L, C, transistor, diode, etc), but they could also go to =3D
>higher or
>lower levels of abstraction.  If they wish, they could write equations =
=3D
>for
>the electron behavior in the crystal structure with all kinds of =
quantum
>effects, etc., but they could also do as IBIS does and write equations =
=3D
>for
>larger building blocks, if they like.  IT IS ALL UP TO THE MODEL =
WRITER.
>
>Another one of the advantages of AMS over SPICE is that we can also =3D
>write
>truly digital equations, and mix them in with analog equations.  These =
=3D
>can
>simplify and speed up the modeling and simulation of logic equations =
and =3D
>state
>machines tremendously, compared with their analog counterparts.
>
>I agree, writing AMS equations may not be for everyone, but it doesn't =
=3D
>have
>to be.  To illustrate this from the SPICE world, another example comes =
=3D
>to my
>mind.  Think about how many people actually write those so-called =3D
>process files.
>(Remember, a SPICE transistor primitive is useless by itself without =
the
>underlying process parameters).  Well, in my company there is a special =
=3D
>group
>of a handful of people who does that, while there are probably several =
=3D
>thousand
>of circuit designers who write schematics.  This discussion thread made =
=3D
>it seem
>that SPICE is easy because it is so familiar, yet no one mentioned that =
=3D
>none of
>those thousands of people designing circuits would get anywhere without =
=3D
>those few
>who provide the most important part of all, the process files!  Also, =
if =3D
>this
>wasn't such a sensitive subject, I could probably tell horror stories =
=3D
>about what
>happens when they don't get it right, because no one using SPICE knows =
=3D
>how to
>fix those parameters...
>
>I see a similar distribution of work in AMS.  There will be a few =
people =3D
>who
>will be able to write templates, primitives, and there will be lots of =
=3D
>people
>who will be using them.
>
>Arpad Muranyi
>Intel Corporation
>=3D3D=3D3D=3D3D=3D3D=3D3D=3D3D=3D3D=3D3D=3D3D=3D3D=3D3D=3D3D=3D3D=3D3D=3D=
3D=3D3D=3D3D=3D3D=3D3D=3D3D=3D3D=3D3D=3D3D=3D3D=3D3D=3D
>=3D3D=3D3D=3D3D=3D3D=3D3D=3D3D=3D3D=3D3D=3D3D=3D3D=3D3D=3D3D=3D3D=3D3D=3D=
3D=3D3D=3D3D=3D3D=3D3D=3D3D=3D3D=3D3D=3D3D=3D3D=3D3D=3D
>=3D3D=3D3D=3D3D=3D3D=3D3D=3D3D=3D3D=3D3D=3D3D=3D3D=3D3D=3D3D=3D3D=3D3D=3D=
3D=3D3D=3D3D=3D3D=3D3D=3D3D=3D3D=3D3D=3D3D=3D3D=3D3D=3D
>=3D3D=3D3D=3D3D
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--=20
-------------------------------------------------------------------------=
--
      |           |         Abdulrahman Rafiq =20
     :|:         :|:        Hardware/IO-Interconnect Modeling Engineer
    :|||:       :|||:       DSW-Interconnect and Packaging
 .:|||||||:...:|||||||:.    Direct: (408) 527-5540
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[SI-LIST] Re: package SSN model accuracy requirements, now Behavioral Modeling

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