[SI-LIST] Re: need advice on DDR3 simulation / termination
- From: "Ken Cantrell" <ken@xxxxxxxxxxxxxxxx>
- To: <joel@xxxxxxxxxx>, "'SI-List'" <si-list@xxxxxxxxxxxxx>
- Date: Fri, 25 Apr 2014 14:43:31 -0600
Joel,
Look at the Jedec spec for DDR3 first, and see what it's supposed to be. In
DDR3, the add/cmd/ctrl are terminated (flyby), but the DQ/DQS are not. Are
you doing DIMMs or down memory ? I would question the reference design, and
ask if this was empirically determined. There could be multiple reasons,
i.e., interfacing to more parts than just the memory, that might require
this irregular termination.
Ken
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On
Behalf Of Joel Brown
Sent: Friday, April 25, 2014 1:07 PM
To: SI-List
Subject: [SI-LIST] need advice on DDR3 simulation / termination
I am working on a DDR3 design.
It uses an older FPGA (Altera Arria II GX) which does does not support ODT
or OCT so all termination has to be external.
The company who is providing the FPGA and IP has a reference design where
the termination is 56 ohms to VTT at the midpoint of the data lines and DQS
lines. I have been trying to simulate this and getting some strange results.
With the DDR3 using Micron's IBIS model driving the line and Altera's
SSTL15 as the receiver the waveform is severely distorted. If I replace
Altera's SSTL15 input with just a 10K resistor it looks much better. I don't
know why the Altera's model for the receiver would cause the distortion
since it should be high impedance with some small parasitics.
Driving the other direction looks better but I get some high frequency
ringing.
I can send screen shots if it helps.
Thanks
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